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Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13μm CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill 0.18μm wide and 0.5μm deep trenches with void free. Through optimizing source/bias RF power, process gas flow and cross section verification, as a result, we got a robust gap-fill recipe with void free.

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