There is a great demand to fabricate polycrystalline silicon films at low temperatures. A metal-induced crystallization method can significantly decrease the crystallization temperature of amorphous silicon (a-Si). Metal thin films are generally deposited on a-Si by the physical vapor deposition method followed by crystallization at a temperature lower than 600°C. In this study, a faster and more inexpensive electroless Ni plating method was introduced. It was found that Si crystallinity increased with Ni plating time, but dropped when the time reached 10 min. When the plating time was less than 5 min, all of the poly-Si became needlelike with preferred orientation parallel to the substrate.

Influences of silicon nitride (SiNx) films on the electrical performances of hydrogenated amorphous silicon thin film transistors (a-Si : H TFTs) are studied. Relatively low temperature (200 °C) SiNx films are prepared by plasma enhanced chemical vapour deposition at different radio-frequency powers. Results indicate that the SiNx films at a radio-frequency power of 340 W (Power density = 1.96 × 10−1 W cm−2) are near-stoichiometric and have better interface quality. Therefore, a-Si : H TFTs with this SiNx gate dielectric layer have a high field effect mobility and sustain the bias stress. The field effect mobility is 0.59 cm2 V−1 s−1 and the threshold voltage shift after a constant voltage stress (CVS) for 2.8 h is 3.18 V. The electrical degradation mechanism of a-Si : H TFTs is studied from the capacitance–voltage measurement. The degradation of the a-Si : H TFT after CVS is due to the defect generation in the SiNx gate dielectric and a-Si : H active layers. However, when the surface roughness of the SiNx film is poor, the degradation from the a-Si : H/SiNx interface is predominated. Therefore, if the SiNx film is used as a gate dielectric layer to fabricate a-Si : H TFTs, the surface roughness and chemical composition of the SiNx film should be considered simultaneously.

A 4.1‐inch flexible QVGA AMOLED display with microcrystalline silicon (μc‐Si:H) TFTs backplane on colorless polyamide (PI) substrate is demonstrated. The PI substrate has the features of high Tg (∼350°C) and high light transmittance (∼90%). The bottom‐gate μc‐Si:H TFTs backplane is fabricated at 200°C by a conventional (13.56 MHz) plasma‐enhanced chemical vapor deposition (PECVD) system. The flexible μc‐Si:H TFTs backplane shows better electrical stability, flexibility, and uniformity.

The growth mechanism of a hybrid process to crystallize amorphous silicon (a-Si) film was studied. In the process, a-Si was first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (NILC), and then annealed with an excimer laser (ELA). Two regions based on different crystallization mechanisms were found on these NILC-ELA films: (A) a-Si melting region, and (B) a-Si/poly-Si melting region. In the a-Si melting region, the sizes and shapes of the needle Si grains were similar to those of NILC poly-Si. In the a-Si/poly-Si melting region, the shapes and sizes of poly-Si grains were quite different from those of NILC needlelike grains. Two crystallization regimes were found in the a-Si/poly-Si melting region: (1) geometrical coalescence regime and (2) complete melting regime. In the geometrical coalescence regime, the width of grains dramatically increased to 600 nm due to the geometrical coalescence of Si needle grains. However, in the complete melting regime, the NILC Si films melted completely. Small poly-Si grains were formed by homogeneous nucleation and growth.

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