A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on (110)-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2nm have been demonstrated, with substantial enhancement of pFET drive current at L,&8Gnm. IntroductionIt is known that hole mobility is more than doubled on (110) silicon substrates with current flow direction along <1 lo> [I -31 compared with conventional (1 00) substrates. However electron mobility is the highest on (100) substrates (Fig. I). To fully utilize the advantage of the carrier mobility dependence on surface orientation, in the present work we have developed a new technology to fabricate CMOS on hybrid substrates with different crystal orientations, with nFETs on silicon of (100) surface orientation and pFETs on (1 IO) surface orientation. High performance CMOS devices using 90nm technology with physical gate oxide thickness as thin as 1.2nm have been demonstrated. Significant pFET enhancement has been achieved.

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We demonstrate a 0.08 pm CMOS suitable for highperformance (vdd=1.8 V) and low-power applications (vdd < 1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for Leff down to 0.06 pm in the NFET and 0.08 pm in the PFET. Aggressive lateral and vertical dopant engineering allow the V, to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at Vd,=l V over the regular-VT process. INTRODUCTION AND DESIGN CRITERIADevice channel lengths are continually scaled to improve circuit performance and packing density. In addition to performance, the emergence of battery-powered applications have emphasized the need for good low-voltage operation. The primary goal for a high-performance sub-0.1 pm device design is to achieve the highest current drive for a given amount of short-channel effect or off-current. At reduced supply voltages, the threshold voltage must also be scaled to maintain adequate performance [l]. To maximize the functionality of a technology, the device design should be suitable for both high-performance and low-power applications with minor modifications. A major challenge is to maintain good short-channel effects in the low-v, case. To achieve these design goals, the following features are used: 1) super-steep retrograde channel; 2) different V,' s for highperformance and low-voltage applications by altering the channel dose; 3) 3.5 nm N 2 0 gate dielectric to improve performance and prevent boron penetration in the PFET; and (4) aggressive lateral dopant engineering to achieve good short-channel effects even at low V,'S.