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Rationale: Thumb function is one of the most fundamental components of hand function, and a vast majority of hand functions are derived from thumb motion. Injury of the thumb interphalangeal joint has a tremendous impact on the function of the thumb, and damage to the thumb interphalangeal joint (IPJ) caused by trauma is usually accompanied by dislocation of the surrounding skin; therefore, it is particularly important to restore the thumb anatomy and skin coverage. Patient concerns: A 41-year-old woman presented with IPJ disfigurement accompanied by a local skin defect caused by machine compression of her right thumb. Restoring the appearance and function of the thumb is key to this operation. Diagnoses: Open fracture of the right thumb. Interventions: After detailed preoperative and radiographic evaluation, the appearance and function of the thumb were reconstructed by IPJ grafting and artificial dermis covering. Outcomes: At 4 months’ follow-up, the patient's visual analogue score was 0, no complications (eg, osteomyelitis, osteolysis, osteoarthritis, and nonunion of the artificial dermis) were observed, and the range of motion of the thumb IPJ returned to 60% of that of the healthy side. Lessons: The innovative application of the second toe proximal IPJ flap combined with double-layer artificial dermis covering to reconstruct the thumb IPJ defect not only solves the problem of skin defects in the recipient area after transplantation in previous cases but also restores the beauty of the recipient area, making it easier for patients to accept this surgical program.

New tendencies envisage multiprocessor systems-onchips (MPSoCs) as a promising solution for the high performance Embedding System. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its extensibility and power efficiency. The router is the fundamental unit of NoC. In this paper, a NoC prototype which consists of 6 ARM compatible cores and a router-based on-chip network is designed, and implements on a FPGA device. Different from the prototypes which we formerly designed, this prototype comprises more cores, and virtual-channel routers instead of basic routers. Specially, to evaluate the network performance, we present a run-time network monitor system, which can monitor the performance of on-chip network by calculating the performance parameters, such as average latency and throughput. The experimental results show that this prototype with 2x3 virtualchannel routers has less average latency than the former basic router prototype, and improves the throughput by up to 62%. Furthermore, JPEG decoding application is applied on this prototype, which steadily works at 50MHZ. And the decoding speed of system is very fast because of 2 decoding lane.

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