The explosive growth and adoption of Smartphones in the mobile market has led to its proliferation into feature-rich phones. Prismark's estimate of total handset shipped globally in 2012 stands at 1.8 Billion (B) units, with Smartphones taking 700 Million (M) unit share, and the projected total market size by 2013 is at 2.3B units. More importantly, the projected Compounded Average Annual Growth Rate (CAAGR) for Smartphone tier is at 21% whiles the projected CAAGR for the historic feature-rich and low-end phone through the same timeframe is -8% and -6%, respectively. As a result of this growth rate increase in Smartphones, adoption of Package-on-Package (PoP) technology, which has long been reserved for high-end phones, and which also benefits from the vertical integration of DRAM memory package and Logic or Application Processor (AP) package, has been increasing mainly due to its capability of addressing the board space limitation faced with, in most Smartphone devices. Additionally, this vertical integration, which results in shorter signal path between the Memory and AP device, leads to better Signal Integrity (SI) and faster data-rate transfer, hence improving the overall device performance. With the more widespread adoption of Smartphones, two other trends have simultaneously been taking place that include downward cost pressure and thinner profile handsets. This latter trend in thickness reduction has long been putting pressure on PoP height reduction, which in turn has resulted in development of various PoP technologies to address the thinner profile package requirements [1]. One particular PoP package type known as Molded Laser-Via Package (MLP) has become popular over the traditional Bare Die PoP type in addressing this height reduction due to its advantages for height reduction and improved warpage performance [2]. However, to address the cost sensitive handset segment and to provide a low cost PoP solution for lower tier Smartphones, recently Bare Die PoP in a very thin profile measuring only to 1.2mm max stack height and with 0.4mm Memory Interface (MI) pitch has been developed and qualified. This paper describes the features of this package, proliferation of Bare Die PoP into larger body packages and challenges that body size-increase brings about, performance comparison of Bare Die PoP to its more advanced MLP counterpart, and some advancements seen in MLP package technology.

Package-On-Package (PoP) is now a wide-spread 3D package technology used in Smartphones, TABLET devices, and in some Gaming applications. The vertical integration of high speed memory packages such as DDR-II and form factor reduction are the main drivers for adoption of these package types. Continuous trends in bump pitch reduction and performance improvement in combination with higher density Si have created the need for Cu column design for Flip Chip bumps. Also, adoption of Cu column and the associated Bond-on-Lead (BoL) technology provide substrate cost reduction through design rule relaxation, which is key for cost sensitive PoP packages and consumer electronics, in general.

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fcCuBE TM technology by STATSChipPAC has gained significant momentum due to several benefits it offers, namely; Bump Pitch (BP) reduction capability with Cucolumn interconnect, cost reduction as a results of substrate design rule relaxation associated with Bond-On-Lead (BOL) and Open Solder Resist (SR) design, and advanced FAB node compatibility due to significant reduction of stress on Extreme low-K (ELK) die-electric layers. Additionally it can result in further cost reduction for special case applications that can benefit from substrate layer count reduction [2], as well those cases that require conversion of wire bond die to flip chip design through the elimination of the costly RDL process that otherwise would be needed for such conversion [5]. With the benefits described above in terms of technology and cost, and the common trend of pitch reduction seen across devices in virtually all market segments including Networking, Mobile devices, Computing, and Consumer Electronics, the adoption of this technology is becoming more widespread.This paper illustrates the feasibility and extendibility of the fcCuBE technology to advanced Si-nodes (28N) and fine pitch applications using the conventional reflow process down to 80um Bump Pitch (BP) and adoption of ThermoCompression Bonding (TCB) process for sub-80um BP to cater to extremely small bump diameters and increased sensitivity to unit warpage and surface non-planarities. In defining the Cu column application space for advanced FAB nodes and fine pitch flip chip packages, a number of design configurations have been considered and qualified. One such configuration describes the development activity using a full functional 28nm Si with Cu column at 140um BP and BOL design where all reliability tests have successfully passed in side-by-side comparison to the Lead-Free (LF) solder bump design version with Solder-On-Pad (SOP). Integration of Cu column with BOL design is evaluated in 28nm Si node where the improved ILD (Inner Layer Dielectric) crack margin gained by BOL design is proven through reliability tests and multiple reflow (Hammer test) studies in side-by-side comparison to the LF solder bump version of the same 28nm TV. Process characterization on 80um BP Daisy Chain (DC) TV using the conventional reflow process is also demonstrated with successful reliability results to prove the process extendibility of fcCuBE with conventional reflow process. In parallel, process characterization of fcCuBE technology using thermo-compression bonding (TCB) process is also demonstrated using sub-80u BP DC TV, thus ensuring the compatibility of fcCuBE technology across the entire spectrum of fine pitch Flip chip applications.