Advancements in Package-on-Package (PoP) technology, delivering performance, form factor & cost benefits in next generation Smartphone processors

Abstract

The explosive growth and adoption of Smartphones in the mobile market has led to its proliferation into feature-rich phones. Prismark's estimate of total handset shipped globally in 2012 stands at 1.8 Billion (B) units, with Smartphones taking 700 Million (M) unit share, and the projected total market size by 2013 is at 2.3B units. More importantly, the projected Compounded Average Annual Growth Rate (CAAGR) for Smartphone tier is at 21% whiles the projected CAAGR for the historic feature-rich and low-end phone through the same timeframe is -8% and -6%, respectively. As a result of this growth rate increase in Smartphones, adoption of Package-on-Package (PoP) technology, which has long been reserved for high-end phones, and which also benefits from the vertical integration of DRAM memory package and Logic or Application Processor (AP) package, has been increasing mainly due to its capability of addressing the board space limitation faced with, in most Smartphone devices. Additionally, this vertical integration, which results in shorter signal path between the Memory and AP device, leads to better Signal Integrity (SI) and faster data-rate transfer, hence improving the overall device performance. With the more widespread adoption of Smartphones, two other trends have simultaneously been taking place that include downward cost pressure and thinner profile handsets. This latter trend in thickness reduction has long been putting pressure on PoP height reduction, which in turn has resulted in development of various PoP technologies to address the thinner profile package requirements [1]. One particular PoP package type known as Molded Laser-Via Package (MLP) has become popular over the traditional Bare Die PoP type in addressing this height reduction due to its advantages for height reduction and improved warpage performance [2]. However, to address the cost sensitive handset segment and to provide a low cost PoP solution for lower tier Smartphones, recently Bare Die PoP in a very thin profile measuring only to 1.2mm max stack height and with 0.4mm Memory Interface (MI) pitch has been developed and qualified. This paper describes the features of this package, proliferation of Bare Die PoP into larger body packages and challenges that body size-increase brings about, performance comparison of Bare Die PoP to its more advanced MLP counterpart, and some advancements seen in MLP package technology.

Implementation and Performance Evaluation of a Bivariate Cut-HDMR Metamodel for Semiconductor Packaging Design Problems with a Large Number of Input Variables

“…The details of design variables are summarized in Table 3. The design spaces of the package dimensions and the material properties were defined by the values found in the literature: package dimensions in [31,[33][34][35][36][37][38][39] and material properties in [40][41][42][43][44][45]. The TFBGA package was subjected to the EMC molding process at 175 • C, which was used as a stress-free temperature.…”

Package-on-Package (PoP) warpage characteristic and requirement

“…Dynamic warpage is common terminology used to describe such behavior. There are many measurement tools that are used to measure the dynamic warpage of the package as listed in [10]. The most common tool made available for this study is the thermal shadow moiré tool.…”

“…PoP is widely used in mobile devices due to its integrated design, lower cost and faster time to market [10]. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost.…”

Thermal performance and fatigue life prediction of POP stacked chip assembly under thermal cycling load

“…With the rapid development of electronic packaging technology, more and more package on package (POP) system products has been widely used, such as smartphone, laptop and so on. We have paid more and more attention to the reliability of the POP stacked chip assembly (Eslampour et al, 2013;Yang et al, 2019;Yang et al, 2014b). Thermal cycling is thought to be the main cause of package fatigue failure (Chen et al, 2015;Zhang et al, 2017).…”