The transition from a planar to a FinFET device structure has changed device doping requirements. The fin sidewall doping and activation, crystallinity control of the fin, junction profile and leakage control on the fin are new challenges. With continuous scaling of FinFET technology, the narrower fins become more prone to crystallinity damage by ion implant, and lead to increases in junction leakage and fin parasitic resistance. We have introduced hot implant as a superior doping technique to room-temperature implant for arsenic source drain extension (SDE) and halo implants on vertical narrow fins. We have demonstrated for the first time that hot SDE implant on 6nm CD vertical fins produced single crystalline fins and enabled 5x improvement in fin line resistance and more than 10x reduction in junction leakage compared with a room-temperature SDE implant.

In this paper, we first review the trends for advanced CMOS devices in terms of architectures and scalability. The paper highlights the key process challenges for planar MOSFET and FinFET device technologies. We emphasize the need for advanced implant solutions to enable device scaling and performance as well as variability improvement. Especially, we discuss the latest damage engineering solutions as well as materials modification techniques (e.g., contact and strain engineering) to reduce leakage, improve drive current and process margin with reduced variability. Finally, we briefly discuss the implications and new challenges coming from novel channel material devices (e.g., silicon-germanium, germanium, and III-V).

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The fundamental design goals for a high-performance logic technology, maximizing speed while minimizing power, drive the design of the junctions and in turn the requirements on dopant placement and activation. In the early nodes implant energies of tens of keV and furnace anneals sufficed. Scaling into the deep submicron regime brought transient enhanced diffusion to the forefront and necessitated its control. This gave rise to rapid thermal annealing and low energy implants. The requirements of current high-performance logic technologies can only be satisfied with careful defect engineering and a further reduction in thermal budget at increased annealing temperatures: flash or laser annealing. Those almost diffusionless anneals make implant precision, such as angle control, imperative. Simultaneously, productivity requirements of implanters add molecular clusters to the list of implant species and lead for certain applications to a switch from beam line to plasma implantation.