An effective interface engineering method is developed to improve performance of SrTiO 3 -based hetero-oxide transistors. HfO 2 /SrTiO 3 hetero-oxide transistors made on argon ions bombarded SrTiO 3 surfaces show eight times increase in drive currents and more than five times increase in mobility when compared with the un-bombarded HfO 2 /SrTiO 3 transistors. The improvement is attributed to the Fermi-level shift as the results of the bombardment. These HfO 2 /SrTiO 3 -based nMOSFETs show field-effect electron mobility up to 4.2 cm 2 /Vs, which is among the best results ever reported.Index Terms-Argon bombardment, channel doping, HfO 2 /SrTiO 3 , MOSFET, oxide.

In this brief, we find that the previously reported performance improvement of HfO 2 /SrTiO 3 devices after argon bombardment may be attributed to the decrease of interface traps. With the greatly reduced interface trap density, the HfO 2 /SrTiO 3 device after argon bombardment shows remarkable reduction of turn-ON voltage shift with decreasing temperature, which is in contrast with the unbombarded HfO 2 /SrTiO 3 device. Though HfO 2 /SrTiO 3 devices behave like conventional transistors, Al 2 O 3 /SrTiO 3 devices show very different linear transfer characteristics, which may be due to the high density of shallow donor states near the Al 2 O 3 /SrTiO 3 interface. The exhibited SrTiO 3 -based device characteristics are studied by experiments and simulations. The simulations with drift-diffusion model reproduce the experimental results.Index Terms-Al 2 O 3 /SrTiO 3 , HfO 2 /SrTiO 3 , interface traps, oxygen vacancy, transistors.

We propose a novel backgate sandwich nanowire MOSFET (SNFET), which offers the advantages of ETSOI (dynamic backgate voltage controllability) and nanowire FETs (good short channel effect). A backgate is used for threshold voltage (Vt) control of the SNFET. Compared with a backgate FinFET with a punch-through stop layer (PTSL), the SNFET possesses improved device performance. 3D device simulations indicate that the SNFET has a three times larger overdrive current, a ∼75% smaller off leakage current, and reduced subthreshold swing (SS) and DIBL than those of a backgate FinFET when the nanowire (NW) and the fin are of equal width. A new process flow to fabricate the backgate SNFET is also proposed in this work. Our analytical model suggests that Vt control by the backgate can be attributed to the capacitances formed by the frontgate, NW, and backgate. The SNFET devices are compatible with the latest state-of-the-art high-k/metal gate CMOS technology with the unique capability of independent backgate control for nFETs and pFETs, which is promising for sub-22 nm scaling down.