Conduction Mechanism in SrTiO&lt;sub&gt;3&lt;/sub&gt;-Based Field-Effect Transistors

Zhu, Zijing; Xu, Jie; Zhao, Hengliang; Luo, Zhijiong

doi:10.1109/ted.2015.2433256

Cited by 22 publications

(8 citation statements)

References 13 publications

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“…SrTiO 3 . [20] As shown in this figure, the HKSD device with the higher ε D has a higher BV. It is obvious that the HKSD device with n = 2 is more easily affected by ε D , but with a high ε D , the BV approaches equality.…”

Section: Optimizations and Discussionmentioning

confidence: 65%

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Yao¹,

Guo²,

Zhang³

et al. 2020

Chinese Phys. B

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This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R on, sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R on, sp compared to the SD device and HK device.

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Section: Optimizations and Discussionmentioning

confidence: 65%

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Yao¹,

Guo²,

Zhang³

et al. 2020

Chinese Phys. B

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“…10 gives the simulation results about the influence of ε D on the BV, R on,sp , and FOM of the STFP-LDMOS. The permittivity value of 3.9, 50, 100, and 200 are corresponding to the high-k materials of SiO 2 , ZrTiO 4 [13], SrTiO 3 [14], and PZT [15]. According to the simulation results, the optimal L GFP and L DFP are 6µm and 4µm for the STFP-LDMOS with ε D = 3.9, while the optimal L GFP and L DFP are 2µm and 2µm of the STFP-LDMOS with ε D = 50, 100, and 200.…”

Section: Resultsmentioning

confidence: 99%

Numerical Analysis of the LDMOS With Side Triangular Field Plate

Yao

Deng

Guo

et al. 2019

IEEE J. Electron Devices Soc.

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A Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) with side triangular field plate (STFP) is proposed for improving the breakdown voltage (BV) and reducing the specific on-resistance (R on,sp ). The main feature of the novel LDMOS is the STFPs at both ends of the drift region, and they are fabricated into the dielectric pillars. With the introduction of the STFPs, the electric field peaks at the P-well/N-drift and N+/N-drift junctions are reduced effectively. The STFPs together with the dielectric pillars modulate the surface and vertical electric field distributions, which enhances the BV. Meanwhile, the doping concentration of the silicon pillars in the drift region is optimized and thus reduces the R on,sp . The simulation results indicate that the BV of 379 V and the R on,sp of 37.3 m •cm 2 are achieved by the STFP-LDMOS. The figure of merits (FOM) of the STFP-LDMOS is 2.7 times compared with the conventional LDMOS without STFPs. The STFP-LDMOS demonstrates a great trade-off between the R on,sp and BV.

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“…Some comparisons of μ FE versus V th are given in Fig. 23 14,25,34,35,41,[43][44][45][46][47][48][49][50] magnitude at the MIS interface by the conductance method, 51) as plotted in Fig. 24(c).…”

Section: Inserting In Situ Aln Interlayer To Improve Mis-gate Channel...mentioning

confidence: 99%

A review of selective area grown recess structure for insulated-gate E-mode GaN transistors

Yang

Yao

et al. 2019

Jpn. J. Appl. Phys.

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Recess structure is one of the main schemes for insulated-gate E-mode GaN transistors. In this work, selective area growth (SAG) is proposed to fabricate damage-free recess-gate device, and related progresses regarding process optimization and structure evolution have been reviewed. Firstly, the SAG process has been optimized by interface separation (conduction interface and regrowth interface) and n-type Si impurity removal to achieve high-quality AlGaN/GaN heterostructure. Compared to the traditional etching method, the feasibility and superiority of SAG scheme are demonstrated for realizing E-mode Al2O3/GaN MISFET with small Vth hysteresis. Then, by inserting an in situ AlN interlayer, the SAG Al2O3/AlN/GaN MISFET yields improved frequency dispersion and gate channel conduction performances. To further enhance the channel conduction, the SAG partially recess-gate Al2O3/AlGaN/GaN MIS-HFET structure is proposed, by which both high Vth and high-field-effect channel mobility have been achieved. Those results indicate that SAG method gives a perspective way for insulated-recess-gate GaN transistors fabrication.

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Conduction Mechanism in SrTiO<sub>3</sub>-Based Field-Effect Transistors

Cited by 22 publications

References 13 publications

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Numerical Analysis of the LDMOS With Side Triangular Field Plate

A review of selective area grown recess structure for insulated-gate E-mode GaN transistors

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