Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n-and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.As device dimensions continue to shrink into the nanometer length scale regime, fundamental physical limits and economics are likely to hinder further scaling according to Moore's law.1 New strategies including usage of new materials, innovative device architectures, and smart integration schemes are needed to extend the current capabilities beyond the end of the technology roadmap time frame. 2 "Bottom-up" approaches to nanoelectronics that utilize functional electronic nanostructures, 3-5 in particular 1D semiconductor nanowires, have the potential to stretch beyond the limits of traditional top-down manufacturing. However, the usual pick-and-place approaches of manipulating and aligning horizontally lying nanowires to fabricate prototype devices and the stringent lithography requirements have to be overcome before practical realization of integrated nanosystems. Furthermore, lithographic issues become paramount in further scaling of these nanowire-based planar devices, especially in defining ultra-small channel length in field-effect transistors (FETs).A proposed solution to these problems is to grow single crystal 1D nanowires directly on a device substrate with the major nanowire growth axis orthogonal to the substrate plane and to use this nanowire-integrated platform for direct device fabrication. Based upon this vertical generic configuration, an ensemble of nanoscale devices can be realized 6,7 ( Figure S1, Supporting Information). In the present work, we demonstrate the potential of this approach through the realization of a vertical surround-gate field-effect transistor (VSG-FET), which takes advantage of the vertical dimension unlike planar nanowire-based FETs and traditional metaloxide-semiconductor (MOS) FETs. The advantages of this vertical device configuration and enhanced device performance have been ad...
A nanoelectrode array based on vertically aligned multiwalled carbon nanotubes (MWNTs) embedded in SiO 2 is used for ultrasensitive DNA detection. Characteristic electrochemical behaviors are observed for measuring bulk and surface-immobilized redox species. Sensitivity is dramatically improved by lowering the nanotube density. Oligonucleotide probes are selectively functionalized to the open ends of nanotubes. The hybridization of subattomole DNA targets can be detected by combining such electrodes with Ru(bpy) 3 2+ mediated guanine oxidation.
We report a bottom-up approach to integrate multiwalled carbon nanotubes (MWNTs) into multilevel interconnects in silicon integrated-circuit manufacturing. MWNTs are grown vertically from patterned catalyst spots using plasma-enhanced chemical vapor deposition. We demonstrate the capability to grow aligned structures ranging from a single tube to forest-like arrays at desired locations. SiO2 is deposited to encapsulate each nanotube and the substrate, followed by a mechanical polishing process for planarization. MWNTs retain their integrity and demonstrate electrical properties consistent with their original structure.
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