This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

No abstract

Conventional IC packaging requires device chips or dice to be packaged at the same level in a way we generally imagined, while newly developed and thriving 3D IC packaging utilizes skyscraper concept to stack numerous types of device chips with different functions occupying the exact same or similar footprint. This approach not only reduces overall package dimension and thickness, but also improves electronic interconnection performance, as well as provides other advantages like lower power dissipation and greater signal bandwidth. Nevertheless, because of the fact that there were tremendous amounts of money and integration efforts spent on fabrication process development, another variant of 3D IC packaging had started to emerge and rapidly flourished in recent years, and it's been referred to as a hybrid between 2D IC and 3D IC packaging, or more specifically, 2.5D IC packaging. Compared with 3D IC, 2.5D IC possesses the benefits of easier process configuration and lower production cost while maintains similar electrical performance as well as reduces certain obstacles where 3D IC packaging is prone to generate. In this paper, our current development of 2.5D IC packaging was demonstrated and displayed, followed by further elaboration of detailed process flow, including device wafer and interposer wafer fabrication in bumping part of process, intermediate die sawing process, and final die level assembly part of process. During the development stage, there were many challenges we had encountered, such as thin wafer handling, carrier bonding and debonding uniformity, warpage alleviation, material stress control, film delamination, as well as other lesser issues. We have offered and proposed certain approaches to particular challenges and the explanation of these challenges as well as proposed solutions was addressed in this paper to properly demonstrate the progression of our 2.5D IC packaging. IntroductionSemiconductor industry has grown and prospered rapidly in the last few decades. As consumer electronics have quickly produced and bloomed in recent years, the demands from customers or end-users became much crucial and prominent in the advancement of technology and the aspect of marketing. Cellular phones, for example, have inevitably followed this trend and played a transitional role from luxurious apparatus to inexpensive necessities in less than 15 years. Easy-to-carry and compact-size cellular phones have been transformed and evolved to smartphones with larger display, thinner body, and additional integrated functions. In order to achieve this kind of demands transition, innovative packaging technology and process techniques have emerged and greatly evolved lately.Sometime around the beginning of the 1990s, people

No abstract

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.