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A wafer level chip-scale-package (WLCSP) is expected to reduce the manufacturing cost of CSPs, but reliability of a solder joint for a large chip size of about 100 mm 2 without underfill assembly is still in question. To meet this needs, we have developed a highly reliable and low-cost WLCSP named wafer process package phase 2 (WPP-2). The package includes a built-in stress-relaxation layer for reducing the strain of the solder bumps. To lower the manufacturing cost of the package, the stress-relaxation layer is formed by printing. The Young's modulus and the thickness of the stressrelaxation layer were optimized by finite element analysis.

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