The Residue number system (RNS) has been employed for efficient parallel carry-free arithmetic computations in DSP applications. Residue addition is the instrumental component in implementing residue converters and channels in RNS. On the other side Reversible Logic is becoming one of the potential power optimization techniques in Low Power CMOS design. In this research paper we have proposed CMOS implementation of two different reversible logic architectures for 4-bit generic

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