No abstract

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die. Figure 25.3.1 shows a block diagram of the SOC. The radio supports 802.11a/b/g, SSN, EDR BT, and FM receiver. Crystal oscillator, low-power oscillator, RCAL, bandgap, and PMU are all shared between the different radios. The shared logic block decides which radio should get the control of the shared analog blocks in conjunction with the co-existence algorithm. In the 2.4GHz receive path, a Shared LNA (SLNA) is used to receive both WLAN and BT signals. The SLNA drives both WLAN LNA2 and BT LNA. Current-mode signaling is used to maintain signal integrity over long routing channels since the rest of the BT core resides a few millimeters away. The two-stage LNA receive architecture helps maintain optimum cascaded noise performance over slow PVT corners. For the WLAN receiver, single-weight combiners (SWC) are implemented using signalpath cartesian phase-shifters to improve receive sensitivity by 3dB by using an additional antenna [1]. In the transmit path, the BT transmitter has the option to use either the WLAN path for output power up to 20dBm or its low-power legacy BT path for better efficiency. The WLAN 2.4GHz load of the mixer serves as the load for the BT mixer output. Two cascaded common-gate stages are employed to pass the BT transmit signal into the WLAN transmit path. The cascaded common-gate stage enables the 2.4GHz BT Tx signal to be routed over long distance and ensures good reverse isolation. Additional shunt and series switches close to the tapping points are used to minimize the loading effect and increase isolation when both WLAN and BT are transmitting at the same time using separate PAs.To remove the need for external baluns, both SLNA and PA use on-chip transformers to convert differential signals to 50 ohms single-ended. The SLNA uses a common-gate input stage with cross-coupled capacitors for wideband matching and noise cancellation [2]. By utilizing the on-chip transformer, two AC coupling capacitors and two shunt inductors can be removed. The SLNA achieves gain of 26dB, noise figure of 3.5dB, and IIP3 of -2dBm all including loss of the transformer. The PA is a pseudo-differential common-source amplifier with transformer as its load. Tuning capacitors at the load are used to match the PA for maximum power and efficiency [3]. For the input stage, core NMOS transistors are used to get the maximum current gain at the input stage. High-voltage NMOS devices are used for the cascode devices to handle the very large voltage swings at its drain. Care must be given to make sure that the input devices are not subject to higher voltages at their drains than they can handle. ...

Broadcom, Irvine, CAAs wireless transceivers for standards such as Bluetooth and 802.11 become more prevalent, the need for lower-cost solutions becomes increasingly important. In this paper, a fully integrated RF front-end architecture is presented; it offers good RF performance, while requiring no off-chip components. This design uses one on-chip transformer to perform the functions of matching, single-ended to differential conversion, and transmit/receive (T/R) switching. While this architecture can be used in many time division duplex systems, the focus of this paper is on CMOS implementations for the Bluetooth standard.The initial architecture of this front-end is based on an earlier design [1], and uses several off-chip components as shown in Fig. 5.8.1. There are various ways to reduce the number of off-chip components. First, the T/R switch can be brought on chip, although the best reported CMOS switches introduce around 1dB of loss [2]. Also, on-chip transformers can replace the off-chip baluns and matching elements [3]. Another approach shorts the LNA input and PA output with a common matching circuit, although some compromise between the LNA and PA impedance match may have to be made [4].Figure 5.8.2 shows the architecture presented in this paper. It uses a multi-tap integrated transformer with one set of ports on the primary side, and two sets of differential ports on the secondary side. One end of the primary connects to the antenna, acting as an RF input/output (I/O) port, while the other end connects to AC ground. On the secondary side, one set of ports connects to the input of the LNA, while a second set of ports connects to the output of the PA. The center tap of the secondary is connected to V DD , providing both AC ground and a DC current path to the PA. The TX and RX front-ends are coupled to the RF I/O port through their connections to the transformer. T/R switch functionality is achieved by powering down one path when the other is in use. The transformer also performs differential to single-ended conversion for both paths, eliminating the need for separate on-or off-chip baluns.For proper operation of the transformer, each port must be tuned appropriately. The simultaneous loading of the PA, LNA, antenna, as well as die and package parasitics must be factored into the overall transformer design and tuning. Furthermore, the matching at each port must be maintained in both RX and TX modes. At the RF I/O port, series and shunt capacitors are used to bring the impedance to 50Ω. For best performance, both the primary ground and the secondary center tap must provide a good AC ground.The LNA schematic is shown in Fig. 5.8.3, with the core design carried over from previous work [1]. A transformer turns ratio of 7 to 2 is selected in order to provide an appropriately large voltage gain at the LNA input. The transformer windings also act as gate inductors, replacing the off-chip inductors in the old architecture [1]. A high-Q transformer design is used to minimize the series resistance of the winding...

Wireless Integrated Network Sensors (WINS) provide distributed network and Internet access to sensors, controls, and processors that are deeply embedded in equipment, facilities, and the environment. The WINS network is a new monitoring and control capability for applications in transportation, manufacturing, health care, environmental monitoring, and safety and security. WINS combine microsensor technology, low power signal processing, low power computation, and low power, low cost wireless networking capability in a compact system. WINS networks will provide sensing, local control, and embedded intelligent systems in structures, materials, and environments. This paper describes the WINS architecture and WINS technology components including sensor interface and WINS event recognition systems.

No abstract