This paper proposes a wideband 2-5GHz LO phaseshifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering directconversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm 2 .

This paper describes a digital-friendly passives-less time delay cell that generates programmable phase-shifts for downconverting front-end in LO-based beamsteering receiver. Cell design supports 1.5-6.5GHz broadband receiver operation and cell layout occupies an area of only 15x16.5µm 2 including power supply rails and control logic. Simulated in 28nm CMOS technology, delay cell exhibits 6 distinct delay values {3, 3.5, 17, 19, 24, 43}ps consuming at most 220µW@1V.

In this paper we present a 4-element Vivaldi antenna array and beamsteering receiver IC for fifth-generation mobile network (5G) New Radio (NR). The implemented receiver utilizes a delay-based local-oscillator (LO) phase-shift technique for accurate beamsteering, and it exhibits 1 to 2.4 degree phase tuning capability for 2-5 GHz bandwidth accordingly. On-chip delay measurement is performed with pilot signal generation and delay estimation capable of 2 ps accuracy. The IC is fabricated on 28 nm CMOS technology, it occupies an area of 1.4 × 1.4 mm 2 including bonding pads and consumes 22.8 mW at 2 GHz for single receiver path operation. The receiver demonstrates wideband over-the-air reception with the prototype antennas.

A 100 mV, output-capacitorless low-dropout (OCL-LDO) regulator for UHF-RFID System-on-Chip applications is presented in this paper. The regulator utilises a 134nA twostage error amplifier with two high frequency compensation amplifiers to increase the limited PSR of the 10 pF load capacitor. The DC PSR performance is maximized with a feed-forward path in the error amplifier. The circuit is able to provide a maximum load current of 4mA, however a feed-forward PSR mechanism optimises the performance to 1mA load conditions. Due to the added feedback compensation amplifier, the twostage error amplifier does not require additional compensation network.

This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ¦(1 to 15.3) mV while consuming 36.8 nW to 4.4 W from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.