Interferometric gravitational wave detectors with an unequal and time-varying arm length configuration like the Laser Interferometer Space Antenna rely on time-delay interferometry (TDI) for laser frequency noise subtraction. However, the TDI algorithm requires a laser ranging scheme with meter accuracy over a five million kilometer arm length. At the end of each arm only about 100 pW of light power will be detected for gravitational wave measurements and only 1% of this power can be used for laser ranging in order to avoid degradation in the phase stability of the science measurements. Here, we present the first experimental demonstration of such a ranging scheme at 1 pW power levels using a Direct Sequence Spread Spectrum (DS/SS) modulation. This type of modulation also enables optical communication by encoding data with ranging signals and provides significant noise reduction against spurious interfering signals for bidirectional ranging. Experimental results show ranging measurements of 42 cm at 3 Hz and the viability of highly reliable data transfer at several kilobits per second.

Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions. The inherently small laser wavelength allows to measure distance variations with extremely high precision by interfering a reference beam with a measurement beam. The readout of such interferometers is often based on tracking phasemeters, able to measure the phase of an incoming beatnote with high precision over a wide range of frequencies. The implementation of such phasemeters is based on all digital phase-locked loops, hosted in FPGAs. Here we present a precise model of an all digital phase locked loop that allows to design such a readout algorithm and we support our analysis by numerical performance measurements and experiments with analog signals.

Abstract.We present the status of our investigations on the LISA Phasemeter. The new prototype is based on a custom-designed breadboard with four high-speed ADC and two DAC channels, extended readout capabilities and a large FPGA (field programmable gate array). The required main functionalities and performance of the prototype have been demonstrated in laboratory conditions.