The behavior of solar cells and modules under various operational conditions can be determined effectively when their intrinsic parameters are accurately estimated and used to simulate the current-voltage (
I-V
) characteristics. This work proposed a new computational approach based on approximation and correction technique (ACT) for simple and efficient extraction of solar cells and modules parameters from the single-diode model. In this technique, an approximated value of series resistance (
R
s
) was first derived and used to determine the initial value of parallel resistance (
R
p
). Later, the final corrected values of
R
s
and
R
p
were obtained by resubstituting their approximated values in a five-loop iteration using the manipulated equations. For rapid evaluation and validation of the proposed technique, a software application was also created using MATLAB program. The correctness and robustness of the proposed technique was validated on five types of solar cells and modules operated at varied temperatures and irradiances. The lowest RMSE value was achieved for RTC France (7.78937E-4) and PVM 752 GaAs (2.10497E-4) solar cell. The legitimacy of ACT extracted parameters was established using a simple yet competitive implementation approach wherein the performance of the developed technique was compared with several state-of-the-art methods recently reported in the literature.
The
channel width-to-length ratio is an important transistor parameter
for integrated circuit design. Contact diffusion into the channel
during fabrication or operation alters the channel width and this
important parameter. A novel methodology combining atomic force microscopy
and scanning Kelvin probe microscopy (SKPM) with self-consistent modeling
is developed for the nondestructive detection of contact diffusion
on active devices. Scans of the surface potential are modeled using
physically based Technology Computer Aided Design (TCAD) simulations
when the transistor terminals are grounded and under biased conditions.
The simulations also incorporate the tip geometry to investigate its
effect on the measurements due to electrostatic tip–sample
interactions. The method is particularly useful for semiconductor–
and metal–semiconductor interfaces where the potential contrast
resulting from dopant diffusion is below that usually detectable with
scanning probe microscopy.
The effect of anisole / decane binary solvent mixture and the subsequent addition of low wt-% aPS on 6,13-bis(triisopropylsilylethynyl-pentacene (TIPS-pentacene) thin film morphology is investigated by optical microscopy, AFM and UV-vis measurements. We show that, over the composition range anisole/decane of 96/4 to 85/15 wt-%, the solution maintains an azeotropic composition with the boiling point of the binary mixture remaining constant at 152 °C, and the solvent composition remaining constant during evaporation and drying. It was found that addition of up to 20 wt-% decane has little impact on micro-scale crystal morphology but has a significant influence on the growth mode and terrace roughness. The formation of large crystals is explained in terms of the change in solvent, increase in decane content, weakening the solute-solvent interactions and promoting efficient nucleation of the favoured H-aggregates of TIPS-pentacene. The effect of the TIPS-pentacene-aPS ratio up to 20 wt-% for drop-cast thin film was similarly investigated. It is found that addition of aPS has a significant effect on both macroscopic crystal properties such as surface coverage, unity of orientation and long range order. It also changes the surface morphology and layer ordering on the nano-scale.
We report the effect of bias stress on the drain current and threshold voltage of n-channel thin-film transistors based on solution processed In2O3 layers. Application of a positive gate bias for variable time-periods led to displacements of the transfer curves in the positive gate bias direction. On switching off the gate bias, the transfer curves returned close to their pre-stress state on a timescale similar to that when the gate bias was switched on. The time dependence of the threshold voltage shift is described well by a stretched-exponential model. The temporal behaviour of the threshold voltage shifts is consistent with charge trapping as the dominant effect, although some defect formation cannot be ruled out.
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