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We investigated the electroless CoWP/NiB diffusion barrier layer for ultralarge-scale integration (ULSI) interconnection by forming the immobilizing Pd catalyst on an organosilane layer. When the electroless CoWP film was formed directly on a Pd-activated organosilane layer, it became islandlike and did not form a continuous layer. When it was formed on an electroless NiB deposited on a Pd-activated organosilane layer, the electroless CoWP film was uniform and formed a continuous layer 10 nm thick. The transmission electron microscopy images of the interfaces of Cu/CoWP/NiB/SiO2 showed that, at an annealing temperature up to 400°C for 30 min, the interfaces remained unchanged and clear, showing no trace of Cu diffusion into the SiO2 substrate. In-plane X-ray diffraction patterns indicated that the CoWP/NiB film had an amorphous structure and was stable against heat-treatment up to 500°C for 30 min. An evaluation of sheet resistance measurements suggested that the CoWP/NiB film shows appropriate barrier properties for Cu diffusion up to 400°C . The CoWP/NiB film was used as a seed for electroless Cu plating. Trenches 100 nm wide were coated with a 10 nm CoWP/NiB barrier followed by successful trench filling by electroless Cu plating.

A wet process based on electroless deposition is proposed for the formation of a diffusion barrier layer for Cu wiring in ultra-large scale integration ͑ULSI͒ technology. The diffusion barrier layer is formed on a low-dielectric constant ͑low-k͒ inter level film. In this process, a Pd-activated self-assembled monolayer as a seed/adhesion layer was used as a key step to allow electroless deposition on a dielectric film. The effectiveness of this approach was demonstrated by depositing an electroless NiB layer as the diffusion barrier layer. The electrolessly deposited NiB layer showed a uniform surface, a small grain size, and a high adhesion when deposited on various common inter level dielectric materials with low dielectric constant. The electrolessly deposited NiB layer formed on the low-k dielectric film by this method showed a high thermal stability of the effectiveness as a barrier to Cu diffusion at temperatures up to 400°C for 30 min. The electroless process was found to be reproducible and did not affect dielectric properties of the underlying insulator.Copper metal is being used in ultralarge scale integration ͑ULSI͒ technology for integrated circuit ͑IC͒ applications owing to its high electrical conductivity and electromigration resistance. The Cu ULSI technology has been developed through the implementation of the so-called "damascene processes" by IBM. 1,2 However, Cu interconnects could be deteriorated by the diffusion of Cu atoms into the insulator layer and substrates.Forming a layer of diffusion barrier between the Cu and the substrate is one of the effective techniques for preventing this diffusion. Today, in most microelectronics processes, the diffusion barrier layer is formed by a dry process; i.e., physical vapor deposition ͑PVD͒ or chemical vapor deposition ͑CVD͒. Recently, atomic layer deposition ͑ALD͒ is also being investigated for that application.Although PVD methods such as sputtering yield high-quality layers, they have severe problems in producing conformal coatings in high aspect ratio via contacts and trenches measuring the sub-100 nm. On the other hand, CVD and ALD yield excellent conformal layers, but they require special precursors and multichambered equipment. An alternative to such dry processes is a wet deposition process, such as an electrochemical deposition method. The wet process offers a good step coverage on substrates with nano scale trenches and vias, a simple procedure and tool, usually leading to a lower cost per wafer.A few reports are found in the literature on the direct formation of a diffusion barrier layer on a low-k dielectric layer by wet processes. They require an activation seed layer, which is formed by a dry process such as sputtering. The seeding process is followed immediately by electrochemical deposition. Typically, dry activation processes seem to yield satisfactory results, while wet processes appear to be unsuitable for the formation of ultrathin Ni or Co barrier layers. Recently, the formation of a thin electroless Co or Ni diffusion barrier laye...

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An atmospheric line-shaped microplasma source was developed for fine pattern etching, and the dependence of the etching properties on the substrate temperature and the distance between the two outer gas outlets was investigated. There was a sudden increase of the etching rate and a decrease of top width when the substrate temperature was 300°C or more. Auger electron spectroscopy (AES) analysis indicates that oxidation on the line shoulder caused the top width to decrease. By decreasing the distance between the two outer gas outlets from 3 mm to 650 µm, the top width decreased from 441 µm to 234 µm. The gas flow simulation result revealed that there exists a firing limit of SF6 partial pressure from 0.1% to 0.2% in the configuration.