Close-packed planar arrays of nanometer-diameter metal clusters that are covalently linked to each other by rigid, double-ended organic molecules have been self-assembled. Gold nanocrystals, each encapsulated by a monolayer of alkyl thiol molecules, were cast from a colloidal solution onto a flat substrate to form a close-packed cluster monolayer. Organic interconnects (aryl dithiols or aryl di-isonitriles) displaced the alkyl thiol molecules and covalently linked adjacent clusters in the monolayer to form a two-dimensional superlattice of metal quantum dots coupled by uniform tunnel junctions. Electrical conductance through such a superlattice of 3.7-nanometer-diameter gold clusters, deposited on a SiO 2 substrate in the gap between two gold contacts and linked by an aryl di-isonitrile [1,4-di(4-isocyanophenylethynyl)-2-ethylbenzene], exhibited nonlinear Coulomb charging behavior.

A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

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Continued reduction in resistance-capacitance (RC) delays in nano-electronic Cu interconnect structures will require new materials with increasingly lower dielectric constants (i.e. low-k). Significant reductions in RC delay can be achieved by reducing the dielectric constant of the relatively high dielectric constant Cu capping/etch stop layer. However, this risks comprising the required barrier performance of this material to the diffusion of Cu, H 2 O, and other species. In this regard, critical thresholds for the diffusion of water and solvents through low-k a-SiO x C y N z :H dielectrics of varying composition were investigated using a combination of X-ray reflectivity mass density and positronium annihilation lifetime spectroscopy pore size metrologies. It was observed that hermetic low-k a-SiO x C y N z :H dielectrics were achieved only at mass densities >2.0 g/cm 3 and when the pore diameter was less than twice the molecular diameter of water. The implications of these critical nano-porosity thresholds on continued scaling of low-k diffusion barrier and ILD materials are discussed as well as methods for overcoming these limitations.