No abstract

Input vector control has been used to minimize the leakage power consumption of a circuit in sleep state [1]. In this paper, we present a novel heuristic for determining a low leakage vector to be applied to a circuit in sleep state. The heuristic is a greedy search based on the controllability of nodes in the circuit and uses the functional dependencies among cells in the circuit to guide the search. Results on a set of ISCAS and MCNC benchmark circuits show that in all cases our heuristic returns a vector having a leakage within 5% of that of the vector obtained using an extensive random search, with orders of magnitude improvement in computational speed.

No abstract

Pass Transistor Logic (PTL) circuits have been successfully used to implement digital ICs which are smaller, faster, and more energy efficient that static CMOS implementations of the same designs. Thus far, most PTL implementations have been handcrafted; as such, designer acceptance of PTL has been limited. In this paper, we develop efficient algorithms for automated synthesis of high quality PTL designs. Our approach is based on the use of Binary Decision Diagrams (BDDs) to represent logic functions. We present several BDD optimization techniques targeting minimum area PTL implementations. We compare our results with prior work on PTL synthesis; we also provide comparison between synthesized static CMOS and synthesized PTL at the layout level for control logic from a commercial microprocessor.

No abstract