We describe the fabrication and operation of a polysilicon room-temperature memory device. The source-drain current-voltage (I -V ) characteristics of this device, with floating gate, demonstrate periodic current steps as well as hysteresis generic for a memory device. Electron micrographs show that the channel consists of 3-5 nm silicon grains. A model of single charge trapping controlled conduction through the device channel is suggested.

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A high performance surrounding gate transistor (SGT) enabling sufficient static and dynamic retention time of future DRAM cells is presented. For the first time, we demonstrate a fully depleted SGT, that shows no reduction of the retention time due to the transient bipolar effect. This effect potentially prevents DRAM application of fully depleted SGTs and is therefore investigated in detail. Based on experimental results, the impact of the proposed SGT on the scalability and performance of future DRAMS is discussed.

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Formation of cobalt silicide spikes in 0.18 μm complementary metal oxide semiconductor process Metal silicides synthesized by high current metal-ion implantationThe formation of thin ͑Ͻ15 nm͒ cobalt silicide layers on amorphous silicon ͑a-Si͒ has been investigated as a part of a program involving the fabrication of poly-Si-based single electron transistors. Rapid thermal annealing was used to promote the reaction between the a-Si and cobalt metal films. The effects of three most important factors on silicide formation during annealing ͑temperature, temperature ramp rate, and anneal time͒ were studied using both electrical ͑sheet resistance͒ and surface analysis ͑Auger electron spectroscopy͒ techniques. In particular, the impact of temperature ramp rate on silicide formation has been addressed. The optimization of the thin silicide process has been achieved by a statistical analysis. Transmission electron microscopy cross-sectional analysis has been performed to determine the thickness of the film.