A major design objective of portable mass spectrometers is the ability to perform in situ chemical analysis on target samples in their native states in the undisturbed environment. The miniature instrument described here is fully contained in a wearable backpack (10 kg) with a geometry-independent low-temperature plasma (LTP) ion source integrated into a hand-held head unit (2 kg) to allow direct surface sampling and analysis. Detection of chemical warfare agent (CWA) simulants, illicit drugs, and explosives is demonstrated at nanogram levels directly from surfaces in near real time including those that have complex geometries, those that are heat-sensitive, and those bearing complex sample matrices. The instrument consumes an average of 65 W of power and can be operated autonomously under battery power for ca. 1.5 h, including the initial pump-down of the manifold. The maximum mass-to-charge ratio is 925 Th with mass resolution of 1-2 amu full width at half-maximun (fwhm) across the mass range. Multiple stages of tandem analysis can be performed to identify individual compounds in complex mixtures. Both positive and negative ion modes are available. A graphical user interface (GUI) is available for novice users to facilitate data acquisition and real-time spectral matching.

Semiconductor device-based sensing of chemical and biological entities has been demonstrated through the use of micro- and nanoscale field-effect devices and close variants. Although carbon nanotubes and silicon nanowires have been demonstrated as single molecule biosensors, the fabrication methods that have been used for creating these devices are typically not compatible with modern semiconductor manufacturing techniques and their large scale integration is problematic. These shortcomings are addressed by recent advancements in microelectronic fabrication techniques which resulted in the realization of nanowire-like structures. Here we report a method to fabricate silicon nanowires at precise locations using such techniques. Our method allows for the realization of truly integrated sensors capable of production of dense arrays. Sensitivity of these devices to changes in the ambient gas composition is also shown.

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This paper describes a novel technique for the fabrication of surface micromachined thin silicon cantilever beams using merged epitaxial lateral overgrowth (MELO) of silicon and chemical-mechanical polishing (CMP). The objective is to demonstrate the feasibility of using this novel technique for the fabrication of arrays of ultrathin, low-stress, single-crystal silicon cantilever beams for use in ultrahigh sensitivity surface-stress or resonant-frequency-based chemical or biological detection schemes. The process flow used in this work will be described in detail and the issues that were faced during the fabrication will be discussed. Cantilever beams with thickness of 0.3-0.5 m that were 10-25-m wide and 75-130-m long were fabricated. Mechanical characterization of the cantilever beams were performed by measuring their spring constant using the "added mass" method, which also demonstrated the use of these initial structures to detect masses as low as 10-100 pg. Further work is underway to scale the thickness of these beams down to the sub-100-nm regime.[823]Index Terms-Cantilever beam, chemical-mechanical polishing (CMP), merged epitaxial lateral overgrowth, silicon-on-insulator (SOI).

Articles you may be interested inPattern-induced alignment of silicon islands on buried oxide layer of silicon-on-insulator structure Quantum transport in a nanosize silicon-on-insulator metal-oxide-semiconductor field-effect transistor Electrical effects of a single stacking fault on fully depleted thin-film silicon-on-insulator P-channel metal-oxide-semiconductor field-effect transistors Unique method to electrically characterize a single stacking fault in silicon-on-insulator metal-oxide-semiconductor field-effect transistors A new method for silicon-on-insulator ͑SOI͒ is presented that has very few stacking fault defects and produces multiple layers of single crystal silicon surrounded by thermal SiO 2 . The technique requires selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical planarization to form SOI islands stacked in multiple layers. Islands of silicon as small as 150ϫ150ϫ40 nm thick were fabricated. Larger SOI islands in two SOI layers, with grown vertical interconnections between layers, were 5ϫ500ϫ0.1 m. Only one stacking fault was observed in 85 000 m 2 of the first layer and none in the second layer. P-channel metal-oxide-semiconductor field effect transistors with gate lengths of less than ϳ100 nm were fabricated in the thin SOI islands. They had normal current-voltage plot characteristics with less than 0.2 pA/m of leakage current, illustrating the quality of the material in both SOI layers and at the silicon to thermal-oxide interfaces. The devices had measured subthreshold slopes of 76 mV/decade and good saturated current drives.