An 86% electron mobility improvement and over 20% bm.,a, enhancement were demonstrated for a 70nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained8i process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16A nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafen. Self-heating of strained3 CMOS due to the low thermal conductivity SiGe virtual substrate reduces Id..,., by 7% during DC operation.

High Idst enhancement is benefited from novel strained-Si process. However, it might cause reliability problems. Here we revealed the HCI degradation of strained-Si devices, which also can he correlated to I&, were worse than conventional bulk Si devices. Besides, it had high positive temperature coefficient in low voltages. Thus, it would be even worse at the operation voltage. [Keywords: hot carrier degradation, strained-Si, short channel.]

The experimental results regarding to the effects of ultraviolet (UV) light illumination on the characteristics of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's) have been presented. The device parameters of a-Si:H TFT, such as threshold voltage, field-effect mobility, and subthreshold slope, have been degraded by electrical stress and visible light illumination, but substantially improved by UV radiation. This may be attributed to an annealing effect on the dangling-bond defects, involving a number of phonons generated by absorption of high energy UV photons in the a-Si:H TFT channel. It has been also observed that the off-current of a-Si:H TFT decreases remarkably while the on-current changes very little. From the experimental results, we report that the improved on/off current ratio of a-Si:H TFT may be achieved by UV radiation.

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the threshold voltage shifts of a-Si TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the illumination periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

The asymmetric amorphous silicon thin film transistors are fabricated and exposed to various stress environments. A visible light illumination of 200,000 Ix and gate bias of 30 V are applied to both asymmetric and widely used symmetric a-Si TFT's. It is observed that the leakage current of asymmetric structure, where only one electrode is fully overlapped by gate electrode, is much less than that of symmetric one. The visible light illumination as well as gate bias stress do not degrade the leakage current of the asymmetric a-Si TFT's, while the leakage current in die symmetric TFT's are increased considerably due to the stress. Also, the degree of degradation in the threshold voltage, the field effect mobility and the subthreshold slope of asymmetric TFT's are relatively much less than that of conventional symmetric TFT's.