Based on the physics of scattering mechanisms of MOSFET inversion layer carriers at different temperatures and vertical electric fields, a new unified mobility model of wide temperature (77-400 K) and E eff range is proposed for IC simulation. Measurement data taken in a wide range of temperatures and electric fields are compared with the simulation results of a MOSFET current model implementing this new mobility equation. Excellent agreement between the simulation and measurement data is found.

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We present, to ow knowledge, the first published experimental integration of two independent gates on a FinFET. The devices have symmetric gate oxide physical thicknesses of 8.5nm, gate lengths ranging from 0.25p-1 to Spm, and designed fin thicknesses ranging from lOnm to 1OOnm. Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages. IntroductionRecently, the double-gate FET has become a popular device candidate for future generations of CMOS technology [l-31. TheFinFET, a vertically oriented embodiment, has received a great deal of attention htely as a double-gate FET that is more amedble to conventional CMOS processing [4-111. One main feature of the FinFET, is the self-alignment and inherent connection of the front and back gates. Certain circuit applications, such as equivalent wellbias control, Multiple Threshold CMOS (MTCMOS) and analog circuits can benefit from independent control of two isolated gates an the same fully-depleted double-gate FET. Also, using one gate to adjust threshold voltage allows device designers to avoid the dopant fluctuation scaling limit. In order to realize these circuits in a FinFET-based technology, several device design challenges exist. While independent-gate operation has been previously demonstrated in planar DGCMOS devices, with non-or quasi-self-aligned gates [12,13], we believe that this work represents the first integration of fully-self-aligned independent-gate operation in a FinFET based Device Fabrication Starting SO1 wafers contained a 40Onm buried oxide layer and a 340nm device layer. A 43Onm sacrificial thermal Si02 layer was grown and removed to thin the SO1 layer to 15Onm. A 120nm thermal Si02 f i l m was grown as a mask for the silicon fm etch, further th"g the SO1 layer to roughly 1OOnm. Fins of thicknesses ranging from lOnm to lOOnm were written using electron-beam lithography. The hard-mask was etched in a CHF3 plasma RIE, and the SO1 layer was etched down to the buried oxide layer in a Clz plasma RIE to produce the bodies of the FinFETs. A 8.5nm sacrificial Si02 was grown and removed to repair the RIE damaged sidewalk. An identical 8.5nm thermal Si02 was grown for the gate dielectric. 360nm of N' in-situ doped polysilicon was deposited, and polishyYpl.eized to the height of the oxide hard-mask using Chemical Mechanical Polishing (CMP). The polysilicon was recessed 5Onm to ensure isolation across the top of the fin. A 22Onm S i a 4 layer was deposited via PECVD, as a gate electrode mask, and pattemed using DUV lithography. The S i a 4 mask was etched in a CHFiElasma RIE, and the Polysilicon was etched down to the buried oxide using a Cl2 plasma N E to define the gate electrodes. The remaining oxide hard-mask was stripped in HF. At this point in the process, the independent-double gate structure has been formed as shown in Figure 1. An 8.5nm sidewall reoxidation was performed to eliminate gate shorts and to cap the silicon for sowceldrain implantation. A 4OkeV 8el4cm-' Arsenic implant was perform...