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6F2(F: Minimum Feature Size) and 4F2 DRAM cell array technology are proposed to increase the number of gross die per wafer with minimum investment. DRAM with 4F2 cell array can increase the gross die about 70% compared to 8F2 technology (Fig. 1). The cell array transistor for 4F2 DRAM must be vertically oriented because its channel, gate and source/drain region should be integrated in IF2 area [1][2]. This paper suggests a novel VPT(Vertical Pillar Transistor) 4F2 DRAM cell array structure and process, especially, to reduce leakage current. It contains the offset Si to reduce GIDL and Si trimming to obtain a fully depleted thin body. The GIDL and DIBL phenomena are fully analyzed with simulations and experiments. Finally, highly controllable and scalable sub 40 nm 4F2 DRAM cell array was obtained. Device FabricationThe bird's eye view of the VPT cell array located at the cross-points of WLs(Word Line) and BLs(Bit Line) is shown in Fig. 2a. With different spaces between pillars which are l1OF and 0.5F along WL and BL direction, respectively ( Fig. 2b), BL is self aligned to pillars with 0.25F oxide spacer as shown in Fig. 2c. Fig.3 describes detailed process sequence for fabricating VPT structure. After a channel ion implantation, SiN is deposited and patterned with the layout of Fig. 2b. With the patterned SiN as hard mask, a 60 nm offset Si is formed with Si etching followed by oxide spacer formation. After formation of trimmed Si channel by Si etching, followed by Si trimming with H202: NH40H: H20 wet chemical, plasma gate oxidation, gate poly deposition and formation (Fig. 4a) are carried out. After N+ ion implantation and 0.25F oxide spacer formation around the pillar, the sub-Si is etched with SiN and oxide spacer as hard mask. By using 0.25F oxide spacer and 0.5F pillar space, the bottom of pillar patterns are connected in BL direction with N+ diffused layer while isolated in WL direction (Fig. 4b). WL is integrated with damascene process to connect the gate poly-to-gate poly and the storage node contact hole is opened with SiN liftoff process. The final structure of VPT DRAM cell array with metal interconnection is shown in Fig. 5. Results and DiscussionWe simulated VPT structures with and without offset Si as shown in Fig. 6. Because VPT has the protruding storage node, we can improve GIDL characteristics (Fig. 6b) owing to its controllability ofphosphorus doping concentration. To evaluate effect of offset Si on leakage current characteristics, we have made experiment on 20 nm thick pillar transistor for two different offset Si of 30 nm and 60 nm with 1.8E13 cm2 channel boron ion dose (Fig. 7). As can be seen clearly, 60 nm offset Si shows about 1 order lower GIDL than that of 30 nm owing to reduced electric field in gate to storage node overlapped region. It is because the longer offset Si makes lower phosphorus doping under the gate edge lower. In addition, VPT with 60 nm offset Si shows an excellent DIBL of 25 mV/V while that of 30 nm offset Si shows 190 mV/V. In spite of very thin body of 20 nm which ...