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A vertical bi-stable resistor (biristor) composed of In 0.53 Ga 0.47 As was demonstrated for sub-1 V operation. An inherent small bandgap and a scaled base length of 150 nm led to the remarkable reduction in latchup voltage compared to Si(Ge)-based conventional biristors. The epitaxially grown n-p-n structure allowed an abrupt p-n junction, which was also very important to reduce the latchup voltage. Furthermore, the physical mechanism of carrier transport in the InGaAs biristor was explored with TCAD simulations.Index Terms-3-D integration, abrupt junction artificial neural network, epitaxial growth, impact ionization, InGaAs, vertical biristor. I. INTRODUCTIONA LTHOUGH the capacitor-less one-transistor dynamic random-access memory (1T-DRAM) has shown great potential of being able to replace conventional DRAM with a higher packing density beyond 4F 2 , its three-terminal structure suffers from inherent gate reliability issues, such as hot carrier injection. [1], [2] To mitigate these issues, the bistable-resistor abbreviated as "biristor", has been developed. A biristor is an open-based two-channel bipolar junction transistor with a collector-base-emitter structure with a doping profile of either n + -p-n + or p + -n-p + . Biristors have shown promising characteristics with enhanced endurance and reliability for post-DRAM technology applications thanks to their gate-less operation. [3]-[6] Compared to 1T-DRAM, another attractive aspect of biristors is their potential for further cell size reduction thanks to their gate-less structure. In principle, when a biristor is formed vertically, the packing density can be reduced to be as small

A new panel design of circular plastic OLED display compared to conventional rectangular display is presented . For narrow bezel, data line is placed at upper half of a circle bezel and power line is connected to bottom half of a circle bezel.

A mnemonic-opto-synaptic transistor (MOST) that has triple functions is demonstrated for an in-sensor vision system. It memorizes a photoresponsivity that corresponds to a synaptic weight as a memory cell, senses light as a photodetector, and performs weight updates as a synapse for machine vision with an artificial neural network (ANN). Herein the memory function added to a previous photodetecting device combined with a photodetector and a synapse provides a technical breakthrough for realizing in-sensor processing that is able to perform image sensing and signal processing in a sensor. A charge trap layer (CTL) was intercalated to gate dielectrics of a vertical pillar-shaped transistor for the memory function. Weight memorized in the CTL makes photoresponsivity tunable for real-time multiplication of the image with a memorized photoresponsivity matrix. Therefore, these multi-faceted features can allow in-sensor processing without external memory for the in-sensor vision system. In particular, the in-sensor vision system can enhance speed and energy efficiency compared to a conventional vision system due to the simultaneous preprocessing of massive data at sensor nodes prior to ANN nodes. Recognition of a simple pattern was demonstrated with full sets of the fabricated MOSTs. Furthermore, recognition of complex hand-written digits in the MNIST database was also demonstrated with software simulations.

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