Wet processes using organic solvents are gaining a renewed interest for stripping high dose ͑ м 1 ϫ 10 15 atoms . cm −2 ͒ ionimplanted photoresist ͑II-PR͒ in front-end-of-line semiconductor manufacturing because of their excellent selectivity to ultrashallow implanted substrates and novel materials. However, the highly cross-linked resist layer ͑so-called crust͒, formed on the top and sidewalls of the resist has very limited solubility in organic solvents unlike the underlying nonimplanted resist ͑bulk͒. This study investigates the effect of UV pre-and post-treatment on II-PR for enabling its removal by organic solvent. Moreover, the impact of the UV wavelength, dose, and power density on the crust and bulk is presented. Optimal conditions of the UV pre-and post-treatment can be determined. Short ͑ Ͻ 200 nm͒ and long wavelengths ͑300-400 nm͒ at low doses induce more scission of the crust with less cross-linking of the bulk, resulting in higher solubility of the II-PR in organic solvents. Moreover, the short wavelength pretreatment is advised because of its bigger effect on the crust, resulting in significant enhancement of the residue removal. In addition, a post-treatment using short wavelengths has high removal efficiency in contrast to the long wavelengths treatment. Finally, no significant impact of the power density is revealed.

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Removal of SiARC containing photo resist stacks presents significant challenges to conventional plasma dry strip tools. Due to the high Si content (35-45% Si), the SiARC removal process must typically be done with a combination of dry and wet processes or done entirely in an etcher. As both the Dry-Wet-Dry and the Etcher approach to SiARC stack removal are long and high cost processes, a single chamber, dry-only solution to SiARC stack removal is highly desirable. This paper reports the dry strip process developed at Axcelis Technologies, Inc. to remove the SiARC stack layer by layer which results in a residue free oxide substrate.

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Industry consolidation in semiconductor manufacturing, driven by commoditization and decreasing margins, is placing ever increasing pressure on fab productivity. Concomitant technology innovation, shrinking device geometries, the transition to non-planar transistors and novel device structures (such as CIS or IGBT) make yield attainment increasingly challenging. The defect level performance of semiconductor manufacturing equipment, in particular in ion implantation, is one of the critical parameters contributing to overall yield performance. This is evidenced through recent large shifts in both particle and metals requirements from device manufacturers. Traditional implanter design approaches, focused on glitch reduction or beam current modulation, are necessary but insufficient to attain simultaneous compliance of availability, throughput and defect levels.In this paper, a holistic approach to defect control is detailed. Examples of contamination control best practices are described. These are combined into an overarching design for process cleanliness (DfPC) methodology, through identification and mitigation of defect opportunities (particulates, metals). Data from the Purion platform of ion implanters demonstrate that, through application of an integrated, common design method, required defect performance can be attained across multiple ion implant platforms.