In 2002, we reported a CCD image sensor with 260×312 pixels capable of capturing 103 consecutive images at 1,000,000 frames per second (1Mfps) [1]. We named the sensor "ISIS-V2", for In-situ Storage Image Sensor Version 2. 103 memory elements are attached to every pixel; generated image signals were instantly and continuously stored in the in-situ storage without being read out of the sensor. The ultimate high-speed recording was enabled by this parallel recording at all pixels. In 2006, the color version, ISIS-V4, was reported [2]. In 2009, we developed ISIS-V12, a backside-illuminated image sensor mounting the ISIS structure and the CCM, charge-carrier multiplication, on the front side [3]. The CCM is a CCD-specific efficient signal-amplification device. CCM, combined with the BSI structure and cooling, achieved very high sensitivity. The ISIS-V12 was a test sensor intended to prove the technical feasibility of the structure. The maximum frame rate was 250kfps for a charge-handling capacity of Q max =10,000e -and 1Mfps for a reduced Q max . The pixel count was 489×400 pixels. For backside-illuminated (BSI) image sensors, metal wires can be placed on the front surface to increase the frame rate without reducing fill factor or violating uniformity of the pixel configuration. It has been proved by simulations that 100Mfps is achievable by introducing innovative technologies including a special wiring method [4]. We now report on ISIS-V16, developed by incorporating technologies to increase the frame rate with those to achieve very high sensitivity, which was confirmed by evaluation of ISIS-V12. The performance specification of ISIS-V16 is summarized in Fig. 23.4.1. Figure 23.4.2 shows the global planar structure of ISIS-V16. The imaging area is divided into 4 rectangular subareas. A set of driving voltages used in the image-capturing operation, which requires very high frequency, is transferred from the left and right, toward the vertical center-line through metal inner bus lines. The very wide inner bus lines, significantly reduce the resistance. The inner bus lines are connected to the outer metal bus lines with a special shape, named "Thunderbolt bus lines," which also serve to reduce the resistance in transferring the driving voltages.Figs. 23.4.3 and 23.4.4 depict the plane structure, installed on the front side, and a cross-section taken along the A-A' line in Fig. 23.4.3. In Fig. 23.4.4, incident photons generate electron-hole pairs in the thick p -generation layer. The generated electrons travel to the collection gate on the front side to form a signal charge packet. The charge packet is then transferred along an n + CCD channel, which is a memory device extending linearly in a slightly slanted direction to the orthogonal direction to the sheet, as shown in Fig. 23.4.3.In Fig. 23.4.3, a signal charge packet is transferred from the collection gate to the memory CCD channel, carried downward and drained from the drain at the end of the CCD channel. Therefore, a sequence of the latest image signals is always ...