In this paper, a failure analysis case, which uses a dynamic operation technique and MgCdTe (MCT) camera to isolate single scan-chain failed cell is demonstrated. Improved results obtained using the MgCdTe (MCT) camera is compared with traditional Si CCD camera. Scan-chain cell schematic and failure mechanism is also presented to explain why static bias conditions are insufficient to detect this failure.

Voltage contrast(VC) is a popular method for failure site isolation[1]. After study we find some weakness on tradition voltage contrast. This paper presents a new voltage contrast procedure that can conquer the weakness. For a CMOS technology, there are four kinds of contact node were used. They are N+/PW node, P+/NW node , poly gate node and well node. Traditional voltage contrast condition uses constant SEM primary energy like 1KV can not distinguish these four kinds of node well. For example a contact lead to P+/NW will be bright in tradition VC[2], but a contact connected to well will also be bright. It means tradition VC can not distinguish difference between contact lead to P+/NW and contact lead to well. To improve the weakness of the traditional VC, we will present a new Voltage Contrast technique, which could distinguish all contact types in CMOS technology.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

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Dielectric film quality is one of the most important factors that will greatly impact device performance and reliability. Device level electrical analysis techniques for dielectric quality monitoring are highly needed. In this paper we present results using a new electrical AFM mode, scanning Microwave Impedance Microscopy (sMIM), for characterization of device oxide quality and for fault isolation. Devices with poor oxide quality show sMIM nano C-V and dC/dV hysteresis behavior during forward and reverse bias sweep. The sMIM capacitance sensitivity is below 1 aF allowing one to capture C-V spectra from the MOS structure formed by the gate and gate oxide with excellent signal/noise ratio and observe subtle variations between different sites.