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In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.

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Logic diagnosis analyzes scan test failures and produces a list of potential defect locations and types. This information is often used as a starting point for a detailed physical failure analysis (PFA) process that locates the actual physical defect. One important criterion that dictates whether PFA can be performed on a certain die is the physical area of the die over which the potential defect locations reported by diagnosis are spread. While logic diagnosis works with a logic-level abstraction of the design, in this paper we describe the use of additional design layout information during diagnosis to lead to better localization of defects and reduce the area over which potential defect locations are spread. This directly results in more die becoming suitable for PFA. We demonstrate the effectiveness of such “layout-aware” diagnosis for PFA using an industrial case study in which several die from two wafers were diagnosed and 61% and 78% more die became suitable for PFA using layout-aware diagnosis.

Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.