PVC (Passive Voltage Contrast) fault isolation method by using a SEM (Scanning Electron Microscope) has been widely used for isolating the defective mc (metal contact) in the CMOS logic SRAM bit cell array. The low power (LP) processed sram cells are easy to charging under PVC test and it helps isolating defective contacts in the cell. However, some device such as a high speed (HS) sram cell is hard to charging in PVC test by unknown reason. It makes difficulties for isolating defective contacts in the sram cell array. In this paper, our group analyzed the electrical current of each contact in sram cell using a nanoprobing technique and correlated it with PVC charged contact images, respectively. Also, the difference of PVC charging status between LP and HS SRAM are characterized electrically by using a nanoprober. The nanoprobing result indicates that a slight increasing a leakage current of about 10pA can abruptly change the charging brightness from dark to grey. Finally, we can found some clues for making grey contacts of HS SRAM using not only a nanoprobing but also a HRTEM (High Resolution Transmission Electron Microscope) image.

In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.