No abstract

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (Wch) and has the effect of modulating current distribution, resulting in lower Ron,sp and higher transconductance (gm). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (Nd-opt) and further reducing the Ron,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (QGD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the Nd-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces Ron,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the Ron,sp and QGD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.

A deep trench super-junction LDMOS with double charge compensation layer (DC DT SJ LDMOS) is proposed in this paper. Due to the capacitance effect of the deep trench which is known as silicon–insulator–silicon (SIS) capacitance, the charge balance in the super-junction region of the conventional deep trench SJ LDMOS (Con. DT SJ LDMOS) device will be broken, resulting in breakdown voltage (BV) of the device drops. DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con. DT SJ LDMOS device. Therefore, the drift region reaches an ideal charge balance state again. The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply, meanwhile the enlarged on-current region reduces its specific on-resistance. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V, and the R on,sp decreased to 23.7 mΩ·cm2.

No abstract

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow speci c on-resistance (R on,sp ) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (W ch ) and has the effect of modulating current distribution, resulting in lower R on,sp and higher transconductance (g m ). Secondly, the SSGs serve as the eld plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (N d-opt ) and further reducing the R on,sp . Moreover, the SSGs also have the effect of modulating the electric eld distribution to maintain a high breakdown voltage (BV). Meanwhile, gatedrain charge (Q GD ) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the N d-opt . The highly doped N-drift region provides a low-resistance path for the current, which also further reduces R on,sp . Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the R on,sp and Q GD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.LDMOS is reduced by 63%, and the switching losses are signi cantly reduced. So the proposed device achieves an excellent tradeoff between R on,sp and Q GD . Besides, the proposed device is generally applied to medium and low rated voltages, substantially reducing power losses.