Future generation devices with critical dimensions of less than 130 nm will have source/drain areas with junction depths of less than about 70 nm and a sheet resistance of around 3 Ω/sq. Conventional technologies used to form and contact such shallow and low resistance source/drain areas are concluded to no longer be feasible in manufacturing. Elevated source/drain technology is shown to be very attractive for manufacturing sub-130 nm devices. In this article we describe two critical processes to form such elevated source/drains. First, a novel HF-vapor clean chemistry for native oxide removal is described. The etch chemistry uses acetic acid vapor as a catalyst to initiate and control etching with HF vapor. Excellent repeatability and selectivity are achieved. Second, in situ doped selective epitaxial growth (SEG) of Si and SiGe is addressed. The advantages of adding Ge to the epitaxial film are discussed. Issues like microloading and facet formation are also discussed and are demonstrated as solvable. Vacuum integration of the above two mentioned processes eliminates the need for a high temperature H2 bake. The elimination of the H2 bake and the addition of Ge to enable SEG at lower temperatures are demonstrated to substantially decrease the thermal budget, increase throughput, and eliminate queue time in the factory. These improvements make elevated source/drain technology technically and economically feasible for the manufacturing of 130–70 nm devices.

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for "true" SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore® (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of a-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the a-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.

Chemical-vapor-deposition (CVD) conditions were investigated for enabling the growth of pure boron (PureB) on Si with low stress and at as low as possible temperature. The application of the B as masking material for Si wet etching by tetramethyl ammonium hydroxide (TMAH) and as membrane material was demonstrated for B deposition temperatures down to 300 °C. Layer thickness in the range 4 nm to 40 nm was applied. In a Si epitaxy reactor system a close to zero-stress condition was found at ∼600 °C, and in an atomic-layer deposition system operated in CVD mode, loosely-bonded 300 °C layers without measurable stress were realized. The compactness of the layers was evaluated by monitoring the etch rate in standard aluminum wet etchant and by observing electron transmissivity, confirming a clear relationship between deposition conditions, compactness and stress.

The chemical-vapor deposition conditions for the growth of pure boron (PureB) layers on silicon at temperatures as low as 400°C were investigated with the purpose of optimizing photodiodes fabricated with PureB anodes for minimal B-layer thickness, low dark current and chemical robustness. The B-deposition is performed in a commercially-available Si epitaxial reactor from a diborane precursor. In-situ methods commonly used to improve the cleanliness of the Si surface before deposition are tested for a deposition temperature of 450°C and PureB layer thickness of 3 nm. Specifically, high-temperature baking in hydrogen, and exposure to HCl are tested. Both material analysis and electrical diode characterization indicate that these extra cleaning steps degrade the properties of the PureB layer and the fabricated diodes.

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