Enabling technologies for forming and contacting shallow junctions in Si: HF-vapor cleaning and selective epitaxial growth of Si and SiGe

Abstract

Future generation devices with critical dimensions of less than 130 nm will have source/drain areas with junction depths of less than about 70 nm and a sheet resistance of around 3 Ω/sq. Conventional technologies used to form and contact such shallow and low resistance source/drain areas are concluded to no longer be feasible in manufacturing. Elevated source/drain technology is shown to be very attractive for manufacturing sub-130 nm devices. In this article we describe two critical processes to form such elevated source/drains. First, a novel HF-vapor clean chemistry for native oxide removal is described. The etch chemistry uses acetic acid vapor as a catalyst to initiate and control etching with HF vapor. Excellent repeatability and selectivity are achieved. Second, in situ doped selective epitaxial growth (SEG) of Si and SiGe is addressed. The advantages of adding Ge to the epitaxial film are discussed. Issues like microloading and facet formation are also discussed and are demonstrated as solvable. Vacuum integration of the above two mentioned processes eliminates the need for a high temperature H2 bake. The elimination of the H2 bake and the addition of Ge to enable SEG at lower temperatures are demonstrated to substantially decrease the thermal budget, increase throughput, and eliminate queue time in the factory. These improvements make elevated source/drain technology technically and economically feasible for the manufacturing of 130–70 nm devices.

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

“…Ni or Pt), etc. Using SiGe instead of Si might help in incorporating a larger amount of electrically active dopants and reduce, for a given growth rate, the required growth temperature [4,10,12].…”

“…As far as MOSFETs are concerned, the fact that they are aggressively scaled down following the International Technology Roadmap for Semiconductors [2] puts stringent requirements on the source/drain junctions in terms of doping, shallowness and abruptness. One rather elegant method of meeting these prerequisites is to use Si or SiGe raised sources and drains (RSD) selectively grown in the active regions on each side of the gate stack [3][4][5][6][7][8][9][10][11]. This way, very shallow, quite heavily doped junctions can be formed, more material can be used up for silicidation (with, e.g.…”

Selective epitaxial growth of Si and SiGe for metal oxide semiconductor transistors

“…In the last few years, there has been significant interest in SiGe epitaxial growth on silicon substrates, because Si/SiGe heterostructures allow band gap engineering to be used in conjunction with silicon technology [1] in field effect transistors [2,3] and photodetectors [4], for raised sources and drains [5], etc.…”

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

“…Many publications dealing with SEG point out the concern about difficulties related to this type of epitaxy [11,31,32].…”