A bottom-up approach was the key to the successful fabrication of this memory. This approach both minimized the number of processing steps following deposition of the molecular monolayer, as well as protected the molecules from remaining processing steps. In the following paragraphs, we briefly describe the nanofabrication procedures utilized to construct the memory circuit. A full paper describing these procedures in more detail will be submitted for publication in the near future. form an array of top Ti NW electrodes, and the crossbar structure is complete.
A demultiplexer is an electronic circuit designed to separate two or more combined signals. We report on a demultiplexer architecture for bridging from the submicrometer dimensions of lithographic patterning to the nanometer-scale dimensions that can be achieved through nanofabrication methods for the selective addressing of ultrahigh-density nanowire circuits. Order log
2
(
N
) large wires are required to address
N
nanowires, and the demultiplexer architecture is tolerant of low-precision manufacturing. This concept is experimentally demonstrated on submicrometer wires and on an array of 150 silicon nanowires patterned at nanowire widths of 13 nanometers and a pitch of 34 nanometers.
High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm(2) was fabricated by two consecutive imprinting processes.
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