Thermoelectric materials interconvert thermal gradients and electric fields for power generation or for refrigeration. Thermoelectrics currently find only niche applications because of their limited efficiency, which is measured by the dimensionless parameter ZT-a function of the Seebeck coefficient or thermoelectric power, and of the electrical and thermal conductivities. Maximizing ZT is challenging because optimizing one physical parameter often adversely affects another. Several groups have achieved significant improvements in ZT through multi-component nanostructured thermoelectrics, such as Bi(2)Te(3)/Sb(2)Te(3) thin-film superlattices, or embedded PbSeTe quantum dot superlattices. Here we report efficient thermoelectric performance from the single-component system of silicon nanowires for cross-sectional areas of 10 nm x 20 nm and 20 nm x 20 nm. By varying the nanowire size and impurity doping levels, ZT values representing an approximately 100-fold improvement over bulk Si are achieved over a broad temperature range, including ZT approximately 1 at 200 K. Independent measurements of the Seebeck coefficient, the electrical conductivity and the thermal conductivity, combined with theory, indicate that the improved efficiency originates from phonon effects. These results are expected to apply to other classes of semiconductor nanomaterials.

A bottom-up approach was the key to the successful fabrication of this memory. This approach both minimized the number of processing steps following deposition of the molecular monolayer, as well as protected the molecules from remaining processing steps. In the following paragraphs, we briefly describe the nanofabrication procedures utilized to construct the memory circuit. A full paper describing these procedures in more detail will be submitted for publication in the near future. form an array of top Ti NW electrodes, and the crossbar structure is complete.

We describe a general method for producing ultrahigh-density arrays of aligned metal and semiconductor nanowires and nanowire circuits. The technique is based on translating thin film growth thickness control into planar wire arrays. Nanowires were fabricated with diameters and pitches (center-to-center distances) as small as 8 nanometers and 16 nanometers, respectively. The nanowires have high aspect ratios (up to 10(6)), and the process can be carried out multiple times to produce simple circuits of crossed nanowires with a nanowire junction density in excess of 10(11) per square centimeter. The nanowires can also be used in nanomechanical devices; a high-frequency nanomechanical resonator is demonstrated.