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We report the development of gallium arsenide (GaAs) films grown on V-groove patterned (001) silicon (Si) by metalorganic chemical vapor deposition. This technique can provide an advanced virtual substrate platform for photonic integrated circuits on Si. A low defect density of 9.1 × 106 cm−2 was achieved with the aspect ratio trapping capability of the V-grooved Si and dislocation filtering approaches including thermal cycle annealing and dislocation filter layers. The efficiencies of these dislocation reduction methods are quantified by statistical electron channeling contrast imaging characterization. Meanwhile, different sets of dislocation filtering layers are evaluated and optimized. To further demonstrate the suitability of GaAs on the V-grooved Si technique for Si-based photonic devices, especially for the appealing 1.3 μm quantum dot (QD) lasers, a 7-layer indium arsenide QD structure was grown on both GaAs-on-V-grooved Si and native GaAs substrates. The same photoluminescence intensity and full-width at half-maximum values were observed for both structures. The optimization methodology in this work therefore offers a feasible approach to realize high quality III–V materials on Si for large-scale integration.

We report direct growth of 1550-nm InGaAsP multi-quantum-well (MQW) structures in densely packed, smooth, highly crystalline, and millimeter-long InP nanoridges grown by metalorganic chemical vapor deposition on silicon-on-insulator (SOI) substrates. Aspect-ratio-trapping and selective area growth techniques were combined with a two-step growth process to obtain good material quality as revealed by photoluminescence, scanning electronic microscopy, and high-resolution X-ray diffraction characterization. Transmission electron microscopy images revealed sharp MQW/InP interfaces as well as thickness variation of the MQW layer. This was confirmed by atom probe tomography analysis, which also suggests homogenous incorporation of the various III-V elements of the MQW structure. This approach is suitable for the integration of InP-based nanoridges in the SOI platform for new classes of ultra-compact, low-power, nano-electronic, and photonic devices for future tele- and data-communications applications.