Abstract-In this paper, an advanced histogram-equalization algorithm for contrast enhancement is presented. Histogram equalization is the most popular algorithm for contrast enhancement due to its effectiveness and simplicity. It can be classified into two branches according to the transformation function used: global or local. Global histogram equalization is simple and fast, but its contrast-enhancement power is relatively low. Local histogram equalization, on the other hand, can enhance overall contrast more effectively, but the complexity of computation required is very high due to its fully overlapped sub-blocks.In this paper, a low-pass filter-type mask is used to get a nonoverlapped sub-block histogram-equalization function to produce the high contrast associated with local histogram equalization but with the simplicity of global histogram equalization. This mask also eliminates the blocking effect of nonoverlapped sub-block histogram-equalization. The low-pass filter-type mask is realized by partially overlapped sub-block histogram-equalization (POSHE). With the proposed method, since the sub-blocks are much less overlapped, the computation overhead is reduced by a factor of about 100 compared to that of local histogram equalization while still achieving high contrast. The proposed algorithm can be used for commercial purposes where high efficiency is required, such as camcorders, closed-circuit cameras, etc.

In this paper, we present a new digital signal processor developed for digital camcorder applications. Taking the digital image signal from A/D converter, the signal processor generates luminance and chrominance signals of the image using an efficient RGB interpolation algorithm and histogram accumulation. We propose a low-cost RGB interpolation algorithm that has little image degradation and show the usefulness of histogram accumulation implemented in the signal processor.

The high complexity and the short lifetime of 3D graphics acceleration hardware increase the necessity of an environment for hardware development. For easy modification and fast testing of architecture, a high-level language based environment is desirable. Therefore, in this paper we propose a Graphics Architecture Testing Environment (GATE) that is based on Microsoft Visual C++. GATE models overall graphics hardware architecture through a modular approach, supports OpenGL, and offers easy modification and rapid testing of architecture. It also gathers computational statistics. A layered approach and Hardware Description Macro (HDM) support hardware modeling and architecture modification. Pre-defined types and operations provide statistical information. Several case studies of 3D graphics architecture on GATE show the capability of our environment.

In this paper, we propose an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined rendering engines. Based on this analysis, we propose an energy efficient memory address converter for an SoC-based 3D graphics system with an SDRAM frame buffer. About 30% of energy reduction and 20% of runtime reduction is obtained with the address converter. With dynamic power management feature of SDRAM, the energy gains increase to about 50%. The energy and runtime gains are generated by an access pattern analysis based division and assignment of frame buffer onto multiple memory modules. With this proposed access pattern analysis, a frame buffer system optimization of an IP-based 3D graphics accelerator can be performed at early architecture design level.