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Application Specific Instruction Set Processors (ASIPs) seek for an optimal performance/area/energy trade-off for a given algorithm. In all current design methodologies an architectural model must be first manually created based on designers experience. These models are increasingly refined until the design constraints are met, through several time consuming algorithmic/architecture co-exploration iterations. This paper presents a novel performance estimation approach that shortens the design cycle of existing methodologies by providing an early assessment of the impact of customizations on the achievable performance. The approach does so by eliminating the need for a completely specified architecture, without limiting designer's freedom and without simulating the application repeatedly. Overall, our approach reduces the number of necessary coexploration iterations, thus increasing design productivity. We validate our approach via two different case studies: a butterflyenabled ASIP for Fast Fourier Transform computation and a Connected Components Labeling ASIP for computer vision.

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This paper presents the system-level modeling of a Reconfigurable System on Chip (RSoC) that is being currently developed in our institution. Although there is a wide range of possible applications, our system is initially aiming fruit monitoring system. The proposed RSoC contains a 32-bit RISC microprocessor, reconfigurable structures, analog and digital interfaces, an RF transceiver and an Active Pixel Sensor (APS) matrix whose function will consist basically on image acquisition. The modeling at a high level of abstraction has been used lately in the design and verification of SoCs due to the rising complexity of such systems. Virtual platforms using SystemC description language at Transaction-Level Modeling (TLM) allow efficient simulations including software and hardware. In this work, a preliminary evaluation of a systemlevel description of the RSoC is carried out. A JPEG compression algorithm was mapped and implemented as a case study to test the accuracy of the model. Future implementations will include the description of an RF transceiver and the communication between two RSoCs.