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In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated.

To deal with the floorplan design in a System-on-a-Chip (SOC), we have developed an EDA tool that simultaneuosly considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a Manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is vety fast, this tool can he integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.

To show the effctiveness of our power-planning algorithm, we respectively integrate this algorithm into a non-slicing and a slicing floorplanners, the experimental results showed are veryIn this paper, we introduce a tile-graph-based approach to Power planning. For a given flooplan solution, the power inputs are -."...r".-.... modeled into a tile graph, the minimum capacity of each Power input and the maximum Power need of each module in a floorplan are accumulated in an associated tile. An efficient cost evaluation algorithm is adopted to calculate the COS[ of Power Planning. As ifs computation time is quite short, it is reasonable to integrate such an algorithm into am iterative floorplanning environment. This is organized as follows. Section 2 introduces the formulation. Section 3 describes the algorithm of cost evaluation of local power The experimental results on the floorplanning piatform are presented in Section 4. The last section draws a conclusion,

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