Electronic packaging is increasingly becoming a vital part of the electronics industry, representing a key
barrier to cost reduction and performance improvement. Of all the packaging methods,
flip‐chip technology offers, up to now, the highest packaging density and best electrical
performance. In this paper, flip‐chip test design considerations,
process development and driving forces for adhesive joining and soldering flip‐chip processes
will be given. Reliability test results of flip‐chip interconnection technology using conductive
adhesive joining will also be presented. The electrical contact nature of the adhesive joint will be
elaborated in the light of continuous and static electrical resistance measurement. Future research work directions in flip‐chip joining using eutectic solder and
conductive adhesives on flexible circuits will also be discussed.
The
electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is
going to become the major alternative for future products. The user wants more functionality
and portability at an ever increasing speed and the need for denser packaging is becoming
urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison
between CSP and flip chip is not straightforward, since many CSPs are really flip chips in
small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.
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