ATHENA has been designed as a general purpose detector capable of delivering the full scientific scope of the Electron-Ion Collider. Careful technology choices provide fine tracking and momentum resolution, high performance electromagnetic and hadronic calorimetry, hadron identification over a wide kinematic range, and near-complete hermeticity. This article describes the detector design and its expected performance in the most relevant physics channels. It includes an evaluation of detector technology choices, the technical challenges to realizing the detector and the R&D required to meet those challenges.

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In the Run 3 upgrade of ATLAS experiment, the FELIX (Front-End LInk eXchange) system has been prepared as the interface between front-end electronics and common Data Acquisition (DAQ) systems. Based on a PCIe card hosted in commodity server, FELIX's flexibilty makes it has also been adopted by other experiments, such as the Single-Phase ProtoDUNE (Prototype for the Deep Underground Neutrino Experiment), sPHENIX and CBM experiments. The same PCIe based architecture is proposed for use in the ATLAS HL-LHC (High Luminosity Large Hadron Collider) upgrade and the DUNE experiment. To this end, the next generation of FELIX I/O card FLX-801 has been developed. It supports 25+ Gbps high speed fiber optical links and 16-lane Gen4 PCIe interface. There is an on-card DDR4 module to buffer event data for DUNE experiment. This paper reports on the test results for the demonstrator of this next generation card, with which main functions have been successfully evaluated.

High precision timing distribution is crucial to many large scale cosmology and particle physics experiments. Besides the space and energy information, the accurate timing provides an extra dimension for physics event reconstruction. In the timing distribution system, accurate clock phase measurement is an indispensable tool to monitor the phase drift and to achieve accurate phase adjustment. This paper introduces a novel phase measurement method implemented in the Xilinx Field Programmable Gate Array (FPGA). It uses the dedicated phase interpolator in the multi-gigabit transceiver. A design based on this method is implemented within the Kintex Ultrascale series FPGA. The preliminary test result shows that a sub-picosecond level precision is achieved. With this system, the nonlinearity of the phase adjustment in the Xilinx transceiver is measured.