Shallow-donor levels due to Si, Ge, Sn, S, Se, and Te in GaAs are neutralized by association with atomic hydrogen; Si and Te donors in AlGaAs have also been shown to be neutralized. In contrast, the shallow acceptors Be, Mg, Zn, and Cd in GaAs are relatively unaffected by hydrogenation. The activation energy for recovery of the donor electrical activity is around 2.1 e V for each of the species, but varies as the strength of an isolated hydrogen-donor species bond. The neutralization depth of the donors is proportional to the inverse square root of donor concentration, and this depth is given as a function of plasma exposure temperature ( 100-350 ·C) and bonding site density (8X 10 13 -1.5 X 10 18 cm-3 ).

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This paper discusses initial results from a study of pattern placement errors due to substrate charging in fixed spot direct write electron beam systems. Experimental results obtained from small crosses written with 20 keY electrons near large pads indicate charging~induced errors of 0.2 flm can occur over 1 mm away from the pad. We present a simple theory that describes the placement errors for large cross-pad separations. The theory suggests that the substrate-electron interaction is strong and long range. Finally, we give some insights on how 50 keY electrons effectively reduce charging effects.

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In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.