No abstract

Shallow-Trench Isolation (STI) relies on integrated process optimization to achieve the requirement of chip-level process variation across different device features. Characterization of pattern density dependency was investigated through Chemical Mechanical Polishing (CMP) process optimization by Design of Experiment (DOE) and modification of masks by adding dummy structure. Four mask sets with different device features and pattern densities were tested. Effects of slurry selectivity, over-polish extent, silicon trench depth, high-density plasma film thickness, and dummy structure were evaluated. Correlation between physical and electrical data illustrates the process margin in which both logic and memory devices could perform their respective functions. KEYWORDS: Shallow-Trench Isolation, System-on-a-Chip, Pattern Density, Chemical-Mechanical Polishing.