No abstract

Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16 m. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13m technology node.

Shallow-Trench Isolation (STI) relies on integrated process optimization to achieve the requirement of chip-level process variation across different device features. Characterization of pattern density dependency was investigated through Chemical Mechanical Polishing (CMP) process optimization by Design of Experiment (DOE) and modification of masks by adding dummy structure. Four mask sets with different device features and pattern densities were tested. Effects of slurry selectivity, over-polish extent, silicon trench depth, high-density plasma film thickness, and dummy structure were evaluated. Correlation between physical and electrical data illustrates the process margin in which both logic and memory devices could perform their respective functions. KEYWORDS: Shallow-Trench Isolation, System-on-a-Chip, Pattern Density, Chemical-Mechanical Polishing.