The electrical properties of the silicon dioxide/n-type (100) InP interface were significantly improved by thin interlayers of chemical bath deposited CdS. The CdS layer and CdS/InP interface were investigated with x-ray photoelectron spectroscopy (XPS) and photoluminescence (PL). XPS data showed reduction of native oxides and the prevention of subsequent substrate oxide growth following CdS layer deposition. PL spectra, measured between 1.0 and 1.3 μm, indicate a reduction in phosphorus vacancies. Metal–insulator–semiconductor (MIS) capacitors fabricated with CdS-treated InP substrates displayed interface-state densities below 1×1011 eV−1 cm−2 when determined from the difference between the high- and low-frequency capacitance data.

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Cadmium sulfide (CdS) layers were deposited from an aqueous solution of thiourea, cadmium sulfate, and ammonia on (100) n-InP at 60–95 °C. X-ray photoelectron spectroscopy showed that the deposition process effectively removes native oxides on InP and forms a protective layer for subsequent dielectric deposition. Surface analysis also showed that the InP surface is not P deficient following oxide deposition on CdS-treated InP. Capacitance–voltage and conductance–voltage measurements of metal–insulator–semiconductor (MIS) capacitors were used to compare samples with and without CdS films between InP and a deposited insulator. Capacitance–voltage response of CdS-treated MIS structures showed well-defined regions of accumulation, depletion, and inversion. The interface-state density at midgap was reduced from 5×1011 to 6×1010 eV−1 cm−2 with CdS treatment. Depletion-mode MIS field-effect transistors made using this new passivation technique exhibited superior device performance to that of untreated samples.