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Strain-engineered PMOS devices have been characterized by physical and electrical analysis, and computer modeling. Characteristic defects at the sidewall of embedded SiGe were found to degrade transistor performance. This could be attributed to carrier scattering rather than stress relaxation.

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SRAM stability has been an important topic for the high performance microprocessor industry. There are a several reasons why SRAMs are most susceptible to both process-induced variations and electrical parameter variability. Because the cache cells use devices with minimum gate lengths and widths, process variations become more severe. Sense amplifiers employ matched transistor pairs that are very sensitive to any process variation. This paper focuses on the patterning accuracy of minimum cell devices and of transistors that are meant to be matched. We used and correlated inline CD data, electrical data and lithographic simulations to measure the patterning fidelity of matched pairs.A small cache with failing matched pairs was chosen for the inline CD measurements. The measurements were done on wafers exposed on several scanners to identify their impact on matched pairs. Electrical measurements at especially designed addressable structures were done to verify the inline data. We analyzed the effect of dummy poly and varying line pitches as well as the active width impact on matched pair performance. Based on simulations, a sensitivity analysis for the analyzed layout portion to individual Zernike terms was done. Simulation results are compared with experimental data.Conclusions for the future design of matched transistor pairs and for scanner lens specifications will be given.