One method of miniaturizing electric boards is to reduce the capacitor area on the board. We fabricated a thin film capacitor on a Si wafer, released the capacitor from the wafer, and transferred the released capacitor onto a board. BaTiO 3 (BTO) was chosen as the dielectric material, and a capacitor was fabricated using metal-organic decomposition (MOD) onto a Si wafer with Ti and Pt as the bottom electrode. Measured electric properties included the dielectric constant, at about 640, as the I-V property, and hysteresis. When a BaTiO 3 film was deposited onto the substrate, which had only a Pt electrode (no Ti used for bonding layer) to release from the substrate after deposition, the electrode broke because of internal stress. The stress was measured quantitatively and a new electrode structure was designed to overcome the problem. ECR etching proved adequate for making the electrode structure.

It is useful to be able to further miniaturize printed wiring boards (PWBs) to achieve more compact and multi-functional mobile electronics. Since about 40-50% of the surface of a PWB is covered with passive elements such as capacitors, it is clear that miniaturization would improve performance. On the other hand, PWBs have a low temperature resistance, and thus the boards cannot use capacitors that require higher processing temperatures. The nano-transfer method, which consists of release and transfer steps, solves this problem. After the capacitor is fabricated on a high-temperature-resistant substrate, it is released from the substrate and mounted on the PWB. The purpose of this study is to clarify the release process in order to establish a fabrication technology for embedded substrates.

MEMS devices such as piezoelectric devices are being used for various purposes in recent years. At the same time, silicon wafer diameters have been expanding for the purposes of mass production and cost reduction in the manufacture of these devices. Therefore, it is becoming more difficult to prepare a dielectric film with homogeneous thickness and electrical properties on the wafer. Generally, physical vapor deposition (PVD) methods such as sputtering are said to be comparatively reproducible for preparing films on large wafers, but these methods require expensive equipment. Metal organic decomposition (MOD), a chemical solution deposition (CSD) method, was used to form a PZT (Pb(Zr,Ti)O 3) film on the 4-inch wafers in this study because it does not need expensive equipment such as a vacuum system. To improve the ferroelectric properties of the film formed using the MOD method, we optimized the process parameters using design of experiments methods and found that temperature is the most significant control factor. A PZT film was prepared homogeneously on 4-inch wafers under optimum conditions. Furthermore, a more homogeneous PZT film was prepared by making the temperature uniform using a soaking cover. We think that these results can be applied to the preparation of films on larger wafers as an alternative to PVD methods, which are currently the main method of preparing dielectric films but which require expensive equipment.

High dielectric capacitor, that has around 1000 in dielectric constant, can be successfully formed by nanotransfer on non-heat-resisting substrates. PZT film could be released from the Si substrate and bonded onto the polymer one. The releasing characteristics have the relationships with the thickness of Pt layer. The formed PZT has perovskite structure and clear columnar texture. The proposal of the structure of electrode using Ti is shown in case of the stress film

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