The chips used in modern electronic devices are mainly manufactured and packaged by Outsourced Semiconductor Assembly and Test (OSAT) facilities and are potentially vulnerable to hardware attacks. Due to the complexity of the global supply chain, it is difficult to track the full fabrication process by the foundries or the intellectual property (IP) owners. Additionally, the design for fabricating and packaging the chip made by IP owners remains the same and visible throughout the process. Hence, this design can be seen by every entity in the supply chain using physical inspection techniques, making it vulnerable if any adversaries are present in the supply chain. Security threats such as IP piracy, overbuilding, reverse engineering, and counterfeiting are thus possible by potential adversaries in the supply chain. These attacks have become an increasing concern in the world of trusted microelectronics as supply chain globalization continues to develop. Several security methods have already been developed to protect and detect such threats until they become embedded into sensitive systems, such as logic locking, obfuscating, physically unclonable functions (PUF), and hardware metering. However, these existing prevention methods have their limitations or are not applicable to all devices. In general, only a few existing methods make use of the inherent characteristics of electronic devices and materials to provide reliable security. Hence, novel security and assurance strategies with minimal changes or modifications in the fabrication of the system circuit are urgently required. This paper proposes a novel technique of obfuscation and locking using a reconfigurable nano-electromechanical system (NEMS) based advanced package throughout the supply chain. Using this novel technique, the netlist/golden design for heterogeneously integrated devices will be hidden from malicious adversaries, and the IP designer will have control of its design until it reaches the end-user.

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