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Gate oxide degradation by transient surge current has been tested during polysilicon etching in a parallel-plate plasma-type etcher. To reduce the transient surge current, rf power is removed gradually at a rate of 50 W/s after 50% overetch. Breakdown voltage distribution measured at a metal–oxide–semiconductor capacitor array structure with gate edges is improved considerably by the ramping down of rf power. This clearly indicates that the transient surge current can cause charge damage to some extent even in a plasma-type etcher. Gate oxide recovery during the interpolyoxide deposition is also discussed.

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To overcome C/H(contact holes) shrinkage limitation of Resist Flow Process(RFP), we investigated and analyzed the tendency of the shrink bias according to the baking temperature and other process factors. Based on this basic test, we found that the shrink bias for the baking temperature could be modeled on the simple linear function. And also we estimated new Hotplate to improve CD uniformity after the resist flow and evaluated newly developed photoresist (New Resist) for the stable C/H shrinkage. In this study, we could recognize that CD uniformity after the resist flow was very dependent on actual temperature uniformity of Hotplate. Actually New Hotplate, which was superior to normal Hotplate, showed good CD uniformity(l6nm) at the strong shrink bias(l4Onm). On the other hand, the C/H shrinkage of New Resist was more stable than those of normal KrF Resists and its C/H profiles could not be severely deformed at even high baking temperature to shrink Sub-7Onm C/H from original C/H(200nm). Based on these results, the progressive Resist Flow Process in KrF lithography will be a very robust candidate at even high gigabit generation devices.